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memory: tegra: Add support for a variable-size client ID bitfield
Recent versions of the Tegra MC hardware extend the size of the client ID bitfield in the MC_ERR_STATUS register by one bit. While one could simply extend the bitfield for older hardware, that would allow data from reserved bits into the driver code, which is generally a bad idea on principle. So this patch instead passes in the client ID mask from from the per-SoC MC data. There's no MC support for T210 (yet), but when that support winds up in the kernel, the appropriate soc->client_id_mask value for that chip will be 0xff. Based on an original patch by David Ung <davidu@nvidia.com>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: David Ung <davidu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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commit
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5 changed files with 9 additions and 2 deletions
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@ -42,7 +42,6 @@
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#define MC_ERR_STATUS_ADR_HI_MASK 0x3
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#define MC_ERR_STATUS_SECURITY (1 << 17)
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#define MC_ERR_STATUS_RW (1 << 16)
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#define MC_ERR_STATUS_CLIENT_MASK 0x7f
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#define MC_ERR_ADR 0x0c
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@ -283,7 +282,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
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else
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secure = "";
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id = value & MC_ERR_STATUS_CLIENT_MASK;
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id = value & mc->soc->client_id_mask;
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for (i = 0; i < mc->soc->num_clients; i++) {
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if (mc->soc->clients[i].id == id) {
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@ -410,6 +409,8 @@ static int tegra_mc_probe(struct platform_device *pdev)
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return err;
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}
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WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
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value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
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MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
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@ -944,5 +944,6 @@ const struct tegra_mc_soc tegra114_mc_soc = {
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.num_clients = ARRAY_SIZE(tegra114_mc_clients),
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.num_address_bits = 32,
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.atom_size = 32,
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.client_id_mask = 0x7f,
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.smmu = &tegra114_smmu_soc,
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};
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@ -1032,6 +1032,7 @@ const struct tegra_mc_soc tegra124_mc_soc = {
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.num_clients = ARRAY_SIZE(tegra124_mc_clients),
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.num_address_bits = 34,
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.atom_size = 32,
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.client_id_mask = 0x7f,
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.smmu = &tegra124_smmu_soc,
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.emem_regs = tegra124_mc_emem_regs,
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.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
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@ -1067,6 +1068,7 @@ const struct tegra_mc_soc tegra132_mc_soc = {
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.num_clients = ARRAY_SIZE(tegra124_mc_clients),
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.num_address_bits = 34,
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.atom_size = 32,
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.client_id_mask = 0x7f,
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.smmu = &tegra132_smmu_soc,
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};
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#endif /* CONFIG_ARCH_TEGRA_132_SOC */
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@ -966,5 +966,6 @@ const struct tegra_mc_soc tegra30_mc_soc = {
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.num_clients = ARRAY_SIZE(tegra30_mc_clients),
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.num_address_bits = 32,
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.atom_size = 16,
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.client_id_mask = 0x7f,
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.smmu = &tegra30_smmu_soc,
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};
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@ -102,6 +102,8 @@ struct tegra_mc_soc {
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unsigned int num_address_bits;
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unsigned int atom_size;
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u8 client_id_mask;
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const struct tegra_smmu_soc *smmu;
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};
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