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phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers
Use "regmap" for read and write to Sierra registers. This is in perparation for adding SERDES_16G support present in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Kishon Vijay Abraham I
parent
372428db44
commit
380f57083c
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@ -22,49 +22,63 @@
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#include <dt-bindings/phy/phy.h>
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/* PHY register offsets */
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#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
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#define SIERRA_DET_STANDEC_A (0x4000 << 2)
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#define SIERRA_DET_STANDEC_B (0x4001 << 2)
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#define SIERRA_DET_STANDEC_C (0x4002 << 2)
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#define SIERRA_DET_STANDEC_D (0x4003 << 2)
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#define SIERRA_DET_STANDEC_E (0x4004 << 2)
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#define SIERRA_PSM_LANECAL (0x4008 << 2)
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#define SIERRA_PSM_DIAG (0x4015 << 2)
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#define SIERRA_PSC_TX_A0 (0x4028 << 2)
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#define SIERRA_PSC_TX_A1 (0x4029 << 2)
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#define SIERRA_PSC_TX_A2 (0x402A << 2)
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#define SIERRA_PSC_TX_A3 (0x402B << 2)
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#define SIERRA_PSC_RX_A0 (0x4030 << 2)
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#define SIERRA_PSC_RX_A1 (0x4031 << 2)
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#define SIERRA_PSC_RX_A2 (0x4032 << 2)
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#define SIERRA_PSC_RX_A3 (0x4033 << 2)
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#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
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#define SIERRA_PLLCTRL_GEN_D (0x403E << 2)
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#define SIERRA_DRVCTRL_ATTEN (0x406A << 2)
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#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
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#define SIERRA_RX_CREQ_FLTR_A_MODE1 (0x4087 << 2)
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#define SIERRA_RX_CREQ_FLTR_A_MODE0 (0x4088 << 2)
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#define SIERRA_CREQ_CCLKDET_MODE01 (0x408E << 2)
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#define SIERRA_RX_CTLE_MAINTENANCE (0x4091 << 2)
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#define SIERRA_CREQ_FSMCLK_SEL (0x4092 << 2)
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#define SIERRA_CTLELUT_CTRL (0x4098 << 2)
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#define SIERRA_DFE_ECMP_RATESEL (0x40C0 << 2)
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#define SIERRA_DFE_SMP_RATESEL (0x40C1 << 2)
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#define SIERRA_DEQ_VGATUNE_CTRL (0x40E1 << 2)
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#define SIERRA_TMRVAL_MODE3 (0x416E << 2)
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#define SIERRA_TMRVAL_MODE2 (0x416F << 2)
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#define SIERRA_TMRVAL_MODE1 (0x4170 << 2)
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#define SIERRA_TMRVAL_MODE0 (0x4171 << 2)
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#define SIERRA_PICNT_MODE1 (0x4174 << 2)
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#define SIERRA_CPI_OUTBUF_RATESEL (0x417C << 2)
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#define SIERRA_LFPSFILT_NS (0x418A << 2)
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#define SIERRA_LFPSFILT_RD (0x418B << 2)
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#define SIERRA_LFPSFILT_MP (0x418C << 2)
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#define SIERRA_SDFILT_H2L_A (0x4191 << 2)
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#define SIERRA_COMMON_CDB_OFFSET 0x0
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#define SIERRA_MACRO_ID_REG 0x0
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#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
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((0x4000 << (block_offset)) + \
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(((ln) << 9) << (reg_offset)))
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#define SIERRA_DET_STANDEC_A 0x000
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#define SIERRA_DET_STANDEC_B 0x001
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#define SIERRA_DET_STANDEC_C 0x002
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#define SIERRA_DET_STANDEC_D 0x003
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#define SIERRA_DET_STANDEC_E 0x004
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#define SIERRA_PSM_LANECAL 0x008
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#define SIERRA_PSM_DIAG 0x015
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#define SIERRA_PSC_TX_A0 0x028
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#define SIERRA_PSC_TX_A1 0x029
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#define SIERRA_PSC_TX_A2 0x02A
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#define SIERRA_PSC_TX_A3 0x02B
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#define SIERRA_PSC_RX_A0 0x030
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#define SIERRA_PSC_RX_A1 0x031
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#define SIERRA_PSC_RX_A2 0x032
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#define SIERRA_PSC_RX_A3 0x033
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#define SIERRA_PLLCTRL_SUBRATE 0x03A
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#define SIERRA_PLLCTRL_GEN_D 0x03E
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#define SIERRA_DRVCTRL_ATTEN 0x06A
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#define SIERRA_CLKPATHCTRL_TMR 0x081
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#define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087
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#define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088
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#define SIERRA_CREQ_CCLKDET_MODE01 0x08E
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#define SIERRA_RX_CTLE_MAINTENANCE 0x091
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#define SIERRA_CREQ_FSMCLK_SEL 0x092
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#define SIERRA_CTLELUT_CTRL 0x098
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#define SIERRA_DFE_ECMP_RATESEL 0x0C0
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#define SIERRA_DFE_SMP_RATESEL 0x0C1
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#define SIERRA_DEQ_VGATUNE_CTRL 0x0E1
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#define SIERRA_TMRVAL_MODE3 0x16E
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#define SIERRA_TMRVAL_MODE2 0x16F
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#define SIERRA_TMRVAL_MODE1 0x170
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#define SIERRA_TMRVAL_MODE0 0x171
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#define SIERRA_PICNT_MODE1 0x174
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#define SIERRA_CPI_OUTBUF_RATESEL 0x17C
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#define SIERRA_LFPSFILT_NS 0x18A
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#define SIERRA_LFPSFILT_RD 0x18B
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#define SIERRA_LFPSFILT_MP 0x18C
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#define SIERRA_SDFILT_H2L_A 0x191
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#define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \
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(0xc000 << (block_offset))
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#define SIERRA_PHY_PLL_CFG 0xe
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#define SIERRA_MACRO_ID 0x00007364
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#define SIERRA_MAX_LANES 4
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static const struct reg_field macro_id_type =
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REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
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static const struct reg_field phy_pll_cfg_1 =
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REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
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struct cdns_sierra_inst {
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struct phy *phy;
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u32 phy_type;
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@ -80,28 +94,93 @@ struct cdns_reg_pairs {
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struct cdns_sierra_data {
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u32 id_value;
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u8 block_offset_shift;
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u8 reg_offset_shift;
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u32 pcie_regs;
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u32 usb_regs;
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struct cdns_reg_pairs *pcie_vals;
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struct cdns_reg_pairs *usb_vals;
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};
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struct cdns_sierra_phy {
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struct cdns_regmap_cdb_context {
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struct device *dev;
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void __iomem *base;
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u8 reg_offset_shift;
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};
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struct cdns_sierra_phy {
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struct device *dev;
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struct regmap *regmap;
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struct cdns_sierra_data *init_data;
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struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
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struct reset_control *phy_rst;
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struct reset_control *apb_rst;
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struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
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struct regmap *regmap_phy_config_ctrl;
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struct regmap *regmap_common_cdb;
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struct regmap_field *macro_id_type;
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struct regmap_field *phy_pll_cfg_1;
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struct clk *clk;
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int nsubnodes;
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bool autoconf;
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};
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static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
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{
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struct cdns_regmap_cdb_context *ctx = context;
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u32 offset = reg << ctx->reg_offset_shift;
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writew(val, ctx->base + offset);
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return 0;
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}
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static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct cdns_regmap_cdb_context *ctx = context;
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u32 offset = reg << ctx->reg_offset_shift;
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*val = readw(ctx->base + offset);
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return 0;
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}
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#define SIERRA_LANE_CDB_REGMAP_CONF(n) \
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{ \
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.name = "sierra_lane" n "_cdb", \
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.reg_stride = 1, \
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.fast_io = true, \
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.reg_write = cdns_regmap_write, \
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.reg_read = cdns_regmap_read, \
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}
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static struct regmap_config cdns_sierra_lane_cdb_config[] = {
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SIERRA_LANE_CDB_REGMAP_CONF("0"),
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SIERRA_LANE_CDB_REGMAP_CONF("1"),
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SIERRA_LANE_CDB_REGMAP_CONF("2"),
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SIERRA_LANE_CDB_REGMAP_CONF("3"),
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};
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static struct regmap_config cdns_sierra_common_cdb_config = {
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.name = "sierra_common_cdb",
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.reg_stride = 1,
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.fast_io = true,
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.reg_write = cdns_regmap_write,
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.reg_read = cdns_regmap_read,
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};
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static struct regmap_config cdns_sierra_phy_config_ctrl_config = {
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.name = "sierra_phy_config_ctrl",
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.reg_stride = 1,
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.fast_io = true,
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.reg_write = cdns_regmap_write,
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.reg_read = cdns_regmap_read,
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};
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static void cdns_sierra_phy_init(struct phy *gphy)
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{
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struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
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struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
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struct regmap *regmap = phy->regmap;
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int i, j;
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struct cdns_reg_pairs *vals;
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u32 num_regs;
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@ -115,10 +194,12 @@ static void cdns_sierra_phy_init(struct phy *gphy)
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} else {
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return;
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}
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for (i = 0; i < ins->num_lanes; i++)
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for (j = 0; j < num_regs ; j++)
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writel(vals[j].val, phy->base +
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vals[j].off + (i + ins->mlane) * 0x800);
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for (i = 0; i < ins->num_lanes; i++) {
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for (j = 0; j < num_regs ; j++) {
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regmap = phy->regmap_lane_cdb[i + ins->mlane];
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regmap_write(regmap, vals[j].off, vals[j].val);
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}
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}
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}
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static int cdns_sierra_phy_on(struct phy *gphy)
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@ -159,37 +240,136 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
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static const struct of_device_id cdns_sierra_id_table[];
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static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
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u32 block_offset, u8 reg_offset_shift,
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const struct regmap_config *config)
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{
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struct cdns_regmap_cdb_context *ctx;
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ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return ERR_PTR(-ENOMEM);
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ctx->dev = dev;
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ctx->base = base + block_offset;
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ctx->reg_offset_shift = reg_offset_shift;
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return devm_regmap_init(dev, NULL, ctx, config);
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}
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static int cdns_regfield_init(struct cdns_sierra_phy *sp)
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{
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struct device *dev = sp->dev;
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struct regmap_field *field;
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struct regmap *regmap;
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regmap = sp->regmap_common_cdb;
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field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
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if (IS_ERR(field)) {
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dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
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return PTR_ERR(field);
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}
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sp->macro_id_type = field;
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regmap = sp->regmap_phy_config_ctrl;
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field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
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if (IS_ERR(field)) {
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dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
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return PTR_ERR(field);
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}
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sp->phy_pll_cfg_1 = field;
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return 0;
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}
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static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
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void __iomem *base, u8 block_offset_shift,
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u8 reg_offset_shift)
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{
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struct device *dev = sp->dev;
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struct regmap *regmap;
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u32 block_offset;
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int i;
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for (i = 0; i < SIERRA_MAX_LANES; i++) {
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block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
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reg_offset_shift);
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regmap = cdns_regmap_init(dev, base, block_offset,
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reg_offset_shift,
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&cdns_sierra_lane_cdb_config[i]);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Failed to init lane CDB regmap\n");
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return PTR_ERR(regmap);
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}
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sp->regmap_lane_cdb[i] = regmap;
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}
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regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
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reg_offset_shift,
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&cdns_sierra_common_cdb_config);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Failed to init common CDB regmap\n");
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return PTR_ERR(regmap);
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}
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sp->regmap_common_cdb = regmap;
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block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift);
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regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
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&cdns_sierra_phy_config_ctrl_config);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Failed to init PHY config and control regmap\n");
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return PTR_ERR(regmap);
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}
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sp->regmap_phy_config_ctrl = regmap;
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return 0;
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}
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static int cdns_sierra_phy_probe(struct platform_device *pdev)
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{
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struct cdns_sierra_phy *sp;
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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struct cdns_sierra_data *data;
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unsigned int id_value;
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struct resource *res;
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int i, ret, node = 0;
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void __iomem *base;
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struct device_node *dn = dev->of_node, *child;
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if (of_get_child_count(dn) == 0)
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return -ENODEV;
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/* Get init data for this PHY */
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match = of_match_device(cdns_sierra_id_table, dev);
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if (!match)
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return -EINVAL;
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data = (struct cdns_sierra_data *)match->data;
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sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
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if (!sp)
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return -ENOMEM;
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dev_set_drvdata(dev, sp);
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sp->dev = dev;
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sp->init_data = data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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sp->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(sp->base)) {
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base)) {
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dev_err(dev, "missing \"reg\"\n");
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return PTR_ERR(sp->base);
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return PTR_ERR(base);
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}
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/* Get init data for this PHY */
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match = of_match_device(cdns_sierra_id_table, dev);
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if (!match)
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return -EINVAL;
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sp->init_data = (struct cdns_sierra_data *)match->data;
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ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
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data->reg_offset_shift);
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if (ret)
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return ret;
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ret = cdns_regfield_init(sp);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, sp);
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@ -219,7 +399,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
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reset_control_deassert(sp->apb_rst);
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/* Check that PHY is present */
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if (sp->init_data->id_value != readl(sp->base)) {
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regmap_field_read(sp->macro_id_type, &id_value);
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if (sp->init_data->id_value != id_value) {
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ret = -EINVAL;
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goto clk_disable;
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}
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@ -267,7 +448,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
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/* If more than one subnode, configure the PHY as multilink */
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if (!sp->autoconf && sp->nsubnodes > 1)
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writel(2, sp->base + SIERRA_PHY_PLL_CFG);
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regmap_field_write(sp->phy_pll_cfg_1, 0x1);
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pm_runtime_enable(dev);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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@ -364,6 +545,8 @@ static struct cdns_reg_pairs cdns_pcie_regs[] = {
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static const struct cdns_sierra_data cdns_map_sierra = {
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SIERRA_MACRO_ID,
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0x2,
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0x2,
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ARRAY_SIZE(cdns_pcie_regs),
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ARRAY_SIZE(cdns_usb_regs),
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cdns_pcie_regs,
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