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x86: align per-cpu section to configured cache bytes
This matches the fix for a bug seen on x86-64. Test booted on old hardware that had 32 byte cachelines to begin with. Signed-off-by: Zach Brown <zach.brown@oracle.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
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@ -7,6 +7,7 @@
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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@ -115,7 +116,7 @@ SECTIONS
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__initramfs_start = .;
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.init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { *(.init.ramfs) }
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__initramfs_end = .;
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. = ALIGN(32);
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. = ALIGN(L1_CACHE_BYTES);
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__per_cpu_start = .;
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.data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) { *(.data.percpu) }
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__per_cpu_end = .;
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