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https://github.com/torvalds/linux
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staging: et131x: Remove forward declaration of et131x_adapter_setup
Also associated function movements within et131x.c file Signed-off-by: Mark Einon <mark.einon@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Einon
Greg Kroah-Hartman
parent
44012dfe4e
commit
36f2771a70
1 changed files with 222 additions and 223 deletions
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@ -576,7 +576,6 @@ struct et131x_adapter {
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struct net_device_stats net_stats;
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};
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void et131x_adapter_setup(struct et131x_adapter *adapter);
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void et131x_soft_reset(struct et131x_adapter *adapter);
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void et131x_isr_handler(struct work_struct *work);
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void et1310_setup_device_for_multicast(struct et131x_adapter *adapter);
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@ -1731,6 +1730,53 @@ void et131x_xcvr_init(struct et131x_adapter *adapter)
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}
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}
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/**
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* et131x_configure_global_regs - configure JAGCore global regs
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* @adapter: pointer to our adapter structure
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*
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* Used to configure the global registers on the JAGCore
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*/
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void et131x_configure_global_regs(struct et131x_adapter *adapter)
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{
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struct global_regs __iomem *regs = &adapter->regs->global;
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writel(0, ®s->rxq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
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if (adapter->registry_jumbo_packet < 2048) {
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/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
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* block of RAM that the driver can split between Tx
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* and Rx as it desires. Our default is to split it
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* 50/50:
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*/
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writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
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writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
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} else if (adapter->registry_jumbo_packet < 8192) {
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/* For jumbo packets > 2k but < 8k, split 50-50. */
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writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
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writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
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} else {
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/* 9216 is the only packet size greater than 8k that
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* is available. The Tx buffer has to be big enough
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* for one whole packet on the Tx side. We'll make
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* the Tx 9408, and give the rest to Rx
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*/
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writel(0x01b3, ®s->rxq_end_addr);
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writel(0x01b4, ®s->txq_start_addr);
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}
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/* Initialize the loopback register. Disable all loopbacks. */
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writel(0, ®s->loopback);
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/* MSI Register */
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writel(0, ®s->msi_config);
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/* By default, disable the watchdog timer. It will be enabled when
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* a packet is queued.
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*/
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writel(0, ®s->watchdog_timer);
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}
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/* PM functions */
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/**
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@ -1748,6 +1794,181 @@ int et1310_in_phy_coma(struct et131x_adapter *adapter)
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return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
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}
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/**
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* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
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* @adapter: pointer to our adapter structure
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*/
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void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
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{
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struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
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struct rx_ring *rx_local = &adapter->rx_ring;
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struct fbr_desc *fbr_entry;
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u32 entry;
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u32 psr_num_des;
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unsigned long flags;
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/* Halt RXDMA to perform the reconfigure. */
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et131x_rx_dma_disable(adapter);
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/* Load the completion writeback physical address
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*
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* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
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* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
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* are ever returned, make sure the high part is retrieved here
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* before storing the adjusted address.
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*/
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writel((u32) ((u64)rx_local->rx_status_bus >> 32),
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&rx_dma->dma_wb_base_hi);
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writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo);
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memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
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/* Set the address and parameters of the packet status ring into the
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* 1310's registers
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*/
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writel((u32) ((u64)rx_local->ps_ring_physaddr >> 32),
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&rx_dma->psr_base_hi);
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writel((u32) rx_local->ps_ring_physaddr, &rx_dma->psr_base_lo);
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writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
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writel(0, &rx_dma->psr_full_offset);
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psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
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writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
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&rx_dma->psr_min_des);
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spin_lock_irqsave(&adapter->rcv_lock, flags);
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/* These local variables track the PSR in the adapter structure */
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rx_local->local_psr_full = 0;
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/* Now's the best time to initialize FBR1 contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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}
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/* Set the address and parameters of Free buffer ring 1 (and 0 if
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* required) into the 1310's registers
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*/
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writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
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&rx_dma->fbr1_base_hi);
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writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr1_base_lo);
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writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
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writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
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/* This variable tracks the free buffer ring 1 full position, so it
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* has to match the above.
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*/
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rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
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writel(
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((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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&rx_dma->fbr1_min_des);
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#ifdef USE_FBR0
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/* Now's the best time to initialize FBR0 contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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}
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writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
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&rx_dma->fbr0_base_hi);
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writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr0_base_lo);
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writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
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writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
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/* This variable tracks the free buffer ring 0 full position, so it
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* has to match the above.
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*/
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rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
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writel(
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((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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&rx_dma->fbr0_min_des);
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#endif
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/* Program the number of packets we will receive before generating an
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* interrupt.
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* For version B silicon, this value gets updated once autoneg is
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*complete.
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*/
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writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
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/* The "time_done" is not working correctly to coalesce interrupts
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* after a given time period, but rather is giving us an interrupt
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* regardless of whether we have received packets.
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* This value gets updated once autoneg is complete.
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*/
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writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
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spin_unlock_irqrestore(&adapter->rcv_lock, flags);
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}
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/**
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* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
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* @adapter: pointer to our private adapter structure
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*
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* Configure the transmit engine with the ring buffers we have created
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* and prepare it for use.
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*/
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void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
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{
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struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
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/* Load the hardware with the start of the transmit descriptor ring. */
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writel((u32) ((u64)adapter->tx_ring.tx_desc_ring_pa >> 32),
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&txdma->pr_base_hi);
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writel((u32) adapter->tx_ring.tx_desc_ring_pa,
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&txdma->pr_base_lo);
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/* Initialise the transmit DMA engine */
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writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
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/* Load the completion writeback physical address */
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writel((u32)((u64)adapter->tx_ring.tx_status_pa >> 32),
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&txdma->dma_wb_base_hi);
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writel((u32)adapter->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
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*adapter->tx_ring.tx_status = 0;
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writel(0, &txdma->service_request);
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adapter->tx_ring.send_idx = 0;
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}
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/**
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* et131x_adapter_setup - Set the adapter up as per cassini+ documentation
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* @adapter: pointer to our private adapter structure
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*
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* Returns 0 on success, errno on failure (as defined in errno.h)
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*/
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void et131x_adapter_setup(struct et131x_adapter *adapter)
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{
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/* Configure the JAGCore */
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et131x_configure_global_regs(adapter);
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et1310_config_mac_regs1(adapter);
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/* Configure the MMC registers */
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/* All we need to do is initialize the Memory Control Register */
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writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
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et1310_config_rxmac_regs(adapter);
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et1310_config_txmac_regs(adapter);
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et131x_config_rx_dma_regs(adapter);
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et131x_config_tx_dma_regs(adapter);
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et1310_config_macstat_regs(adapter);
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et1310_phy_power_down(adapter, 0);
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et131x_xcvr_init(adapter);
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}
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/**
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* et1310_enable_phy_coma - called when network cable is unplugged
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* @adapter: pointer to our adapter structure
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@ -2389,121 +2610,6 @@ int et131x_init_recv(struct et131x_adapter *adapter)
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return status;
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}
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/**
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* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
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* @adapter: pointer to our adapter structure
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*/
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void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
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{
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struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
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struct rx_ring *rx_local = &adapter->rx_ring;
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struct fbr_desc *fbr_entry;
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u32 entry;
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u32 psr_num_des;
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unsigned long flags;
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/* Halt RXDMA to perform the reconfigure. */
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et131x_rx_dma_disable(adapter);
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/* Load the completion writeback physical address
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*
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* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
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* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
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* are ever returned, make sure the high part is retrieved here
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* before storing the adjusted address.
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*/
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writel((u32) ((u64)rx_local->rx_status_bus >> 32),
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&rx_dma->dma_wb_base_hi);
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writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo);
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memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
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/* Set the address and parameters of the packet status ring into the
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* 1310's registers
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*/
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writel((u32) ((u64)rx_local->ps_ring_physaddr >> 32),
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&rx_dma->psr_base_hi);
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writel((u32) rx_local->ps_ring_physaddr, &rx_dma->psr_base_lo);
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writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
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writel(0, &rx_dma->psr_full_offset);
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psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
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writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
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&rx_dma->psr_min_des);
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spin_lock_irqsave(&adapter->rcv_lock, flags);
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/* These local variables track the PSR in the adapter structure */
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rx_local->local_psr_full = 0;
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/* Now's the best time to initialize FBR1 contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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}
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/* Set the address and parameters of Free buffer ring 1 (and 0 if
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* required) into the 1310's registers
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*/
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writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
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&rx_dma->fbr1_base_hi);
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writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr1_base_lo);
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writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
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writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
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/* This variable tracks the free buffer ring 1 full position, so it
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* has to match the above.
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*/
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rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
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writel(
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((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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&rx_dma->fbr1_min_des);
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#ifdef USE_FBR0
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/* Now's the best time to initialize FBR0 contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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}
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writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
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&rx_dma->fbr0_base_hi);
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writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr0_base_lo);
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writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
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writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
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/* This variable tracks the free buffer ring 0 full position, so it
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* has to match the above.
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*/
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rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
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writel(
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((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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&rx_dma->fbr0_min_des);
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#endif
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/* Program the number of packets we will receive before generating an
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* interrupt.
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* For version B silicon, this value gets updated once autoneg is
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*complete.
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*/
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writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
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/* The "time_done" is not working correctly to coalesce interrupts
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* after a given time period, but rather is giving us an interrupt
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* regardless of whether we have received packets.
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* This value gets updated once autoneg is complete.
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*/
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writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
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spin_unlock_irqrestore(&adapter->rcv_lock, flags);
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}
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/**
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* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate.
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* @adapter: pointer to our adapter structure
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@ -3045,37 +3151,6 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
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kfree(adapter->tx_ring.tcb_ring);
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}
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/**
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* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
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* @adapter: pointer to our private adapter structure
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*
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* Configure the transmit engine with the ring buffers we have created
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* and prepare it for use.
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*/
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void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
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{
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struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
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/* Load the hardware with the start of the transmit descriptor ring. */
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writel((u32) ((u64)adapter->tx_ring.tx_desc_ring_pa >> 32),
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&txdma->pr_base_hi);
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writel((u32) adapter->tx_ring.tx_desc_ring_pa,
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&txdma->pr_base_lo);
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/* Initialise the transmit DMA engine */
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writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
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/* Load the completion writeback physical address */
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writel((u32)((u64)adapter->tx_ring.tx_status_pa >> 32),
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&txdma->dma_wb_base_hi);
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writel((u32)adapter->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
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*adapter->tx_ring.tx_status = 0;
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writel(0, &txdma->service_request);
|
||||
adapter->tx_ring.send_idx = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
|
||||
* @adapter: pointer to our adapter structure
|
||||
|
|
@ -4021,82 +4096,6 @@ void et131x_error_timer_handler(unsigned long data)
|
|||
TX_ERROR_PERIOD * HZ / 1000);
|
||||
}
|
||||
|
||||
/**
|
||||
* et131x_configure_global_regs - configure JAGCore global regs
|
||||
* @adapter: pointer to our adapter structure
|
||||
*
|
||||
* Used to configure the global registers on the JAGCore
|
||||
*/
|
||||
void et131x_configure_global_regs(struct et131x_adapter *adapter)
|
||||
{
|
||||
struct global_regs __iomem *regs = &adapter->regs->global;
|
||||
|
||||
writel(0, ®s->rxq_start_addr);
|
||||
writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
|
||||
|
||||
if (adapter->registry_jumbo_packet < 2048) {
|
||||
/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
|
||||
* block of RAM that the driver can split between Tx
|
||||
* and Rx as it desires. Our default is to split it
|
||||
* 50/50:
|
||||
*/
|
||||
writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
|
||||
writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
|
||||
} else if (adapter->registry_jumbo_packet < 8192) {
|
||||
/* For jumbo packets > 2k but < 8k, split 50-50. */
|
||||
writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
|
||||
writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
|
||||
} else {
|
||||
/* 9216 is the only packet size greater than 8k that
|
||||
* is available. The Tx buffer has to be big enough
|
||||
* for one whole packet on the Tx side. We'll make
|
||||
* the Tx 9408, and give the rest to Rx
|
||||
*/
|
||||
writel(0x01b3, ®s->rxq_end_addr);
|
||||
writel(0x01b4, ®s->txq_start_addr);
|
||||
}
|
||||
|
||||
/* Initialize the loopback register. Disable all loopbacks. */
|
||||
writel(0, ®s->loopback);
|
||||
|
||||
/* MSI Register */
|
||||
writel(0, ®s->msi_config);
|
||||
|
||||
/* By default, disable the watchdog timer. It will be enabled when
|
||||
* a packet is queued.
|
||||
*/
|
||||
writel(0, ®s->watchdog_timer);
|
||||
}
|
||||
|
||||
/**
|
||||
* et131x_adapter_setup - Set the adapter up as per cassini+ documentation
|
||||
* @adapter: pointer to our private adapter structure
|
||||
*
|
||||
* Returns 0 on success, errno on failure (as defined in errno.h)
|
||||
*/
|
||||
void et131x_adapter_setup(struct et131x_adapter *adapter)
|
||||
{
|
||||
/* Configure the JAGCore */
|
||||
et131x_configure_global_regs(adapter);
|
||||
|
||||
et1310_config_mac_regs1(adapter);
|
||||
|
||||
/* Configure the MMC registers */
|
||||
/* All we need to do is initialize the Memory Control Register */
|
||||
writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
|
||||
|
||||
et1310_config_rxmac_regs(adapter);
|
||||
et1310_config_txmac_regs(adapter);
|
||||
|
||||
et131x_config_rx_dma_regs(adapter);
|
||||
et131x_config_tx_dma_regs(adapter);
|
||||
|
||||
et1310_config_macstat_regs(adapter);
|
||||
|
||||
et1310_phy_power_down(adapter, 0);
|
||||
et131x_xcvr_init(adapter);
|
||||
}
|
||||
|
||||
/**
|
||||
* et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
|
||||
* @adapter: pointer to our private adapter structure
|
||||
|
|
|
|||
Loading…
Reference in a new issue