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crypto: inside-secure - add multiple processing engine support
So far a single processing engine (PE) was configured and used in the Inside Secure SafeXcel cryptographic engine driver. Some versions have more than a single PE. This patch rework the driver's initialization to take this into account and to allow configuring more than one PE. Signed-off-by: Ofer Heifetz <oferh@marvell.com> [Antoine: some reworks and commit message.] Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ofer Heifetz
Herbert Xu
parent
18e0e95b82
commit
367571e43c
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@ -98,7 +98,7 @@ static void eip197_trc_cache_init(struct safexcel_crypto_priv *priv)
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}
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static void eip197_write_firmware(struct safexcel_crypto_priv *priv,
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const struct firmware *fw, u32 ctrl,
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const struct firmware *fw, int pe, u32 ctrl,
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u32 prog_en)
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{
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const u32 *data = (const u32 *)fw->data;
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@ -112,7 +112,7 @@ static void eip197_write_firmware(struct safexcel_crypto_priv *priv,
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EIP197_PE(priv) + ctrl);
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/* Enable access to the program memory */
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writel(prog_en, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL);
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writel(prog_en, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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/* Write the firmware */
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for (i = 0; i < fw->size / sizeof(u32); i++)
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@ -120,7 +120,7 @@ static void eip197_write_firmware(struct safexcel_crypto_priv *priv,
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priv->base + EIP197_CLASSIFICATION_RAMS + i * sizeof(u32));
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/* Disable access to the program memory */
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writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL);
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writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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/* Release engine from reset */
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val = readl(EIP197_PE(priv) + ctrl);
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@ -133,7 +133,7 @@ static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
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const char *fw_name[] = {"ifpp.bin", "ipue.bin"};
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const struct firmware *fw[FW_NB];
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char fw_path[31];
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int i, j, ret = 0;
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int i, j, ret = 0, pe;
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u32 val;
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for (i = 0; i < FW_NB; i++) {
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@ -151,22 +151,26 @@ static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
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}
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}
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/* Clear the scratchpad memory */
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val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL);
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val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
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EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN |
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EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS |
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EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS;
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writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL);
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for (pe = 0; pe < priv->config.pes; pe++) {
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/* Clear the scratchpad memory */
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val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
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val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
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EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN |
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EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS |
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EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS;
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writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
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memset_io(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_RAM, 0,
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EIP197_NUM_OF_SCRATCH_BLOCKS * sizeof(u32));
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memset_io(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_RAM(pe), 0,
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EIP197_NUM_OF_SCRATCH_BLOCKS * sizeof(u32));
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eip197_write_firmware(priv, fw[FW_IFPP], EIP197_PE_ICE_FPP_CTRL,
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EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN);
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eip197_write_firmware(priv, fw[FW_IFPP], pe,
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EIP197_PE_ICE_FPP_CTRL(pe),
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EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN);
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eip197_write_firmware(priv, fw[FW_IPUE], EIP197_PE_ICE_PUE_CTRL,
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EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN);
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eip197_write_firmware(priv, fw[FW_IPUE], pe,
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EIP197_PE_ICE_PUE_CTRL(pe),
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EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN);
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}
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release_fw:
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for (j = 0; j < i; j++)
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@ -262,7 +266,7 @@ static int safexcel_hw_setup_rdesc_rings(struct safexcel_crypto_priv *priv)
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static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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{
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u32 version, val;
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int i, ret;
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int i, ret, pe;
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/* Determine endianess and configure byte swap */
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version = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_VERSION);
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@ -288,82 +292,91 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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/* Clear any pending interrupt */
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writel(GENMASK(31, 0), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
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/* Data Fetch Engine configuration */
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/* Reset all DFE threads */
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writel(EIP197_DxE_THR_CTRL_RESET_PE,
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EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL);
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if (priv->version == EIP197B) {
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/* Reset HIA input interface arbiter */
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writel(EIP197_HIA_RA_PE_CTRL_RESET,
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EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL);
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}
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/* DMA transfer size to use */
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val = EIP197_HIA_DFE_CFG_DIS_DEBUG;
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(6) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(9);
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val |= EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(6) | EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(7);
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val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS);
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val |= EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS);
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writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG);
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/* Leave the DFE threads reset state */
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writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL);
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/* Configure the procesing engine thresholds */
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writel(EIP197_PE_IN_xBUF_THRES_MIN(6) | EIP197_PE_IN_xBUF_THRES_MAX(9),
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EIP197_PE(priv) + EIP197_PE_IN_DBUF_THRES);
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writel(EIP197_PE_IN_xBUF_THRES_MIN(6) | EIP197_PE_IN_xBUF_THRES_MAX(7),
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EIP197_PE(priv) + EIP197_PE_IN_TBUF_THRES);
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if (priv->version == EIP197B) {
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/* enable HIA input interface arbiter and rings */
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writel(EIP197_HIA_RA_PE_CTRL_EN |
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GENMASK(priv->config.rings - 1, 0),
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EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL);
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}
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/* Data Store Engine configuration */
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/* Reset all DSE threads */
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writel(EIP197_DxE_THR_CTRL_RESET_PE,
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EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL);
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/* Wait for all DSE threads to complete */
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while ((readl(EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_STAT) &
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GENMASK(15, 12)) != GENMASK(15, 12))
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;
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/* DMA transfer size to use */
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val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);
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val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
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val |= EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE;
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/* FIXME: instability issues can occur for EIP97 but disabling it impact
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* performances.
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*/
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if (priv->version == EIP197B)
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val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR;
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writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG);
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/* Leave the DSE threads reset state */
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writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL);
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/* Configure the procesing engine thresholds */
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writel(EIP197_PE_OUT_DBUF_THRES_MIN(7) | EIP197_PE_OUT_DBUF_THRES_MAX(8),
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EIP197_PE(priv) + EIP197_PE_OUT_DBUF_THRES);
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/* Processing Engine configuration */
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for (pe = 0; pe < priv->config.pes; pe++) {
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/* Data Fetch Engine configuration */
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/* H/W capabilities selection */
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val = EIP197_FUNCTION_RSVD;
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val |= EIP197_PROTOCOL_ENCRYPT_ONLY | EIP197_PROTOCOL_HASH_ONLY;
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val |= EIP197_PROTOCOL_ENCRYPT_HASH | EIP197_PROTOCOL_HASH_DECRYPT;
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val |= EIP197_ALG_AES_ECB | EIP197_ALG_AES_CBC;
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val |= EIP197_ALG_SHA1 | EIP197_ALG_HMAC_SHA1;
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val |= EIP197_ALG_SHA2 | EIP197_ALG_HMAC_SHA2;
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writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_FUNCTION_EN);
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/* Reset all DFE threads */
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writel(EIP197_DxE_THR_CTRL_RESET_PE,
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EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
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if (priv->version == EIP197B) {
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/* Reset HIA input interface arbiter */
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writel(EIP197_HIA_RA_PE_CTRL_RESET,
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EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));
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}
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/* DMA transfer size to use */
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val = EIP197_HIA_DFE_CFG_DIS_DEBUG;
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(6) |
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EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(9);
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val |= EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(6) |
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EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(7);
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val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS);
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val |= EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS);
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writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG(pe));
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/* Leave the DFE threads reset state */
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writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
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/* Configure the processing engine thresholds */
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writel(EIP197_PE_IN_xBUF_THRES_MIN(6) |
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EIP197_PE_IN_xBUF_THRES_MAX(9),
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EIP197_PE(priv) + EIP197_PE_IN_DBUF_THRES(pe));
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writel(EIP197_PE_IN_xBUF_THRES_MIN(6) |
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EIP197_PE_IN_xBUF_THRES_MAX(7),
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EIP197_PE(priv) + EIP197_PE_IN_TBUF_THRES(pe));
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if (priv->version == EIP197B) {
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/* enable HIA input interface arbiter and rings */
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writel(EIP197_HIA_RA_PE_CTRL_EN |
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GENMASK(priv->config.rings - 1, 0),
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EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));
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}
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/* Data Store Engine configuration */
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/* Reset all DSE threads */
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writel(EIP197_DxE_THR_CTRL_RESET_PE,
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EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
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/* Wait for all DSE threads to complete */
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while ((readl(EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_STAT(pe)) &
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GENMASK(15, 12)) != GENMASK(15, 12))
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;
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/* DMA transfer size to use */
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val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) |
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EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);
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val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
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val |= EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE;
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/* FIXME: instability issues can occur for EIP97 but disabling it impact
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* performances.
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*/
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if (priv->version == EIP197B)
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val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR;
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writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG(pe));
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/* Leave the DSE threads reset state */
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writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
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/* Configure the procesing engine thresholds */
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writel(EIP197_PE_OUT_DBUF_THRES_MIN(7) |
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EIP197_PE_OUT_DBUF_THRES_MAX(8),
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EIP197_PE(priv) + EIP197_PE_OUT_DBUF_THRES(pe));
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/* Processing Engine configuration */
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/* H/W capabilities selection */
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val = EIP197_FUNCTION_RSVD;
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val |= EIP197_PROTOCOL_ENCRYPT_ONLY | EIP197_PROTOCOL_HASH_ONLY;
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val |= EIP197_PROTOCOL_ENCRYPT_HASH | EIP197_PROTOCOL_HASH_DECRYPT;
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val |= EIP197_ALG_AES_ECB | EIP197_ALG_AES_CBC;
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val |= EIP197_ALG_SHA1 | EIP197_ALG_HMAC_SHA1;
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val |= EIP197_ALG_SHA2 | EIP197_ALG_HMAC_SHA2;
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writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_FUNCTION_EN(pe));
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}
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/* Command Descriptor Rings prepare */
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for (i = 0; i < priv->config.rings; i++) {
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@ -414,13 +427,15 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_SIZE);
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}
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/* Enable command descriptor rings */
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writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
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EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL);
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for (pe = 0; pe < priv->config.pes; pe++) {
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/* Enable command descriptor rings */
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writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
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EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
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/* Enable result descriptor rings */
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writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
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EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL);
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/* Enable result descriptor rings */
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writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
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EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
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}
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/* Clear any HIA interrupt */
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writel(GENMASK(30, 20), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
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@ -868,9 +883,20 @@ static void safexcel_unregister_algorithms(struct safexcel_crypto_priv *priv)
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static void safexcel_configure(struct safexcel_crypto_priv *priv)
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{
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u32 val, mask;
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u32 val, mask = 0;
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val = readl(EIP197_HIA_AIC_G(priv) + EIP197_HIA_OPTIONS);
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/* Read number of PEs from the engine */
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switch (priv->version) {
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case EIP197B:
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mask = EIP197_N_PES_MASK;
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break;
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default:
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mask = EIP97_N_PES_MASK;
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}
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priv->config.pes = (val >> EIP197_N_PES_OFFSET) & mask;
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val = (val & GENMASK(27, 25)) >> 25;
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mask = BIT(val) - 1;
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@ -95,13 +95,13 @@
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#define EIP197_HIA_xDR_STAT 0x003c
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/* register offsets */
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#define EIP197_HIA_DFE_CFG 0x0000
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#define EIP197_HIA_DFE_THR_CTRL 0x0000
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#define EIP197_HIA_DFE_THR_STAT 0x0004
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#define EIP197_HIA_DSE_CFG 0x0000
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#define EIP197_HIA_DSE_THR_CTRL 0x0000
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#define EIP197_HIA_DSE_THR_STAT 0x0004
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#define EIP197_HIA_RA_PE_CTRL 0x0010
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#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
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#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
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#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
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#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
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#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
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#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
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#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
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#define EIP197_HIA_RA_PE_STAT 0x0014
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#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
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#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
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@ -114,18 +114,18 @@
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#define EIP197_HIA_MST_CTRL 0xfff4
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#define EIP197_HIA_OPTIONS 0xfff8
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#define EIP197_HIA_VERSION 0xfffc
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#define EIP197_PE_IN_DBUF_THRES 0x0000
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#define EIP197_PE_IN_TBUF_THRES 0x0100
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#define EIP197_PE_ICE_SCRATCH_RAM 0x0800
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#define EIP197_PE_ICE_PUE_CTRL 0x0c80
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#define EIP197_PE_ICE_SCRATCH_CTRL 0x0d04
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#define EIP197_PE_ICE_FPP_CTRL 0x0d80
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#define EIP197_PE_ICE_RAM_CTRL 0x0ff0
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||||
#define EIP197_PE_EIP96_FUNCTION_EN 0x1004
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||||
#define EIP197_PE_EIP96_CONTEXT_CTRL 0x1008
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||||
#define EIP197_PE_EIP96_CONTEXT_STAT 0x100c
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||||
#define EIP197_PE_OUT_DBUF_THRES 0x1c00
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#define EIP197_PE_OUT_TBUF_THRES 0x1d00
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#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
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||||
#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
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||||
#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
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||||
#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
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||||
#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
|
||||
#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
|
||||
#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
|
||||
#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
|
||||
#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
|
||||
#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
|
||||
#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
|
||||
#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
|
||||
#define EIP197_MST_CTRL 0xfff4
|
||||
|
||||
/* EIP197-specific registers, no indirection */
|
||||
|
|
@ -184,6 +184,11 @@
|
|||
#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
|
||||
#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
|
||||
|
||||
/* EIP197_HIA_OPTIONS */
|
||||
#define EIP197_N_PES_OFFSET 4
|
||||
#define EIP197_N_PES_MASK GENMASK(4, 0)
|
||||
#define EIP97_N_PES_MASK GENMASK(2, 0)
|
||||
|
||||
/* EIP197_HIA_AIC_R_ENABLE_CTRL */
|
||||
#define EIP197_CDR_IRQ(n) BIT((n) * 2)
|
||||
#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
|
||||
|
|
@ -513,6 +518,7 @@ struct safexcel_request {
|
|||
};
|
||||
|
||||
struct safexcel_config {
|
||||
u32 pes;
|
||||
u32 rings;
|
||||
|
||||
u32 cd_size;
|
||||
|
|
|
|||
Loading…
Reference in a new issue