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phy: qcom-qmp-pcie: Add RC init sequence for SDX55
Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -1146,6 +1146,41 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
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};
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};
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static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
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};
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static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
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static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
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@ -1225,6 +1260,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
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};
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};
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static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
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};
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static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
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static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
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@ -2308,6 +2348,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
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.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
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.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
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},
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},
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.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
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.serdes = sdx55_qmp_pcie_rc_serdes_tbl,
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.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
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.pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
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.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
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},
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.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
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.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
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.serdes = sdx55_qmp_pcie_ep_serdes_tbl,
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.serdes = sdx55_qmp_pcie_ep_serdes_tbl,
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.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
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.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
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@ -2323,7 +2370,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = pciephy_v4_regs_layout,
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.regs = pciephy_v4_regs_layout,
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.pwrdn_ctrl = SW_PWRDN,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.phy_status = PHYSTATUS_4_20,
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.phy_status = PHYSTATUS_4_20,
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};
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};
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@ -6,6 +6,8 @@
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
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#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
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#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
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#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
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#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
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