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ASoC: Intel: avs: ICCMAX recommendations for ICL+ platforms
For ICL+ platforms to avoid DMI/OPIO L1 entry during the base firmware load procedure, HW recommends to set LTRP_GB to 95us and start an additional CAPTURE stream in the background. Once the load completes, original LTRP_GB value is restored and the additional stream is released. Reviewed-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Link: https://msgid.link/r/20240220115035.770402-10-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -131,6 +131,8 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
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#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
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#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
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#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
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#define AZX_REG_VS_LTRP_GB_MASK GENMASK(6, 0)
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/* PCI space */
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/* PCI space */
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#define AZX_PCIREG_TCSEL 0x44
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#define AZX_PCIREG_TCSEL 0x44
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@ -325,6 +325,8 @@ int avs_hda_load_library(struct avs_dev *adev, struct firmware *lib, u32 id);
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int avs_hda_transfer_modules(struct avs_dev *adev, bool load,
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int avs_hda_transfer_modules(struct avs_dev *adev, bool load,
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struct avs_module_entry *mods, u32 num_mods);
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struct avs_module_entry *mods, u32 num_mods);
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int avs_icl_load_basefw(struct avs_dev *adev, struct firmware *fw);
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/* Soc component members */
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/* Soc component members */
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struct avs_soc_component {
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struct avs_soc_component {
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@ -7,9 +7,13 @@
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//
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//
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <sound/hdaudio.h>
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#include <sound/hdaudio_ext.h>
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#include "avs.h"
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#include "avs.h"
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#include "messages.h"
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#include "messages.h"
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#define ICL_VS_LTRP_GB_ICCMAX 95
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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int avs_icl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
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int avs_icl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
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u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
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u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
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@ -118,6 +122,62 @@ int avs_icl_set_d0ix(struct avs_dev *adev, bool enable)
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return AVS_IPC_RET(ret);
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return AVS_IPC_RET(ret);
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}
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}
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int avs_icl_load_basefw(struct avs_dev *adev, struct firmware *fw)
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{
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struct hdac_bus *bus = &adev->base.core;
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struct hdac_ext_stream *host_stream;
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struct snd_pcm_substream substream;
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struct snd_dma_buffer dmab;
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unsigned int sd_fmt;
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u8 ltrp_gb;
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int ret;
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/*
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* ICCMAX:
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*
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* For ICL+ platforms, as per HW recommendation LTRP_GB is set to 95us
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* during FW load. Its original value shall be restored once load completes.
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*
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* To avoid DMI/OPIO L1 entry during the load procedure, additional CAPTURE
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* stream is allocated and set to run.
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*/
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memset(&substream, 0, sizeof(substream));
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substream.stream = SNDRV_PCM_STREAM_CAPTURE;
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host_stream = snd_hdac_ext_stream_assign(bus, &substream, HDAC_EXT_STREAM_TYPE_HOST);
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if (!host_stream)
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return -EBUSY;
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ltrp_gb = snd_hdac_chip_readb(bus, VS_LTRP) & AZX_REG_VS_LTRP_GB_MASK;
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/* Carries no real data, use default format. */
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sd_fmt = snd_hdac_stream_format(1, 32, 48000);
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ret = snd_hdac_dsp_prepare(hdac_stream(host_stream), sd_fmt, fw->size, &dmab);
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if (ret < 0)
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goto release_stream;
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snd_hdac_chip_updateb(bus, VS_LTRP, AZX_REG_VS_LTRP_GB_MASK, ICL_VS_LTRP_GB_ICCMAX);
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spin_lock(&bus->reg_lock);
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snd_hdac_stream_start(hdac_stream(host_stream));
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spin_unlock(&bus->reg_lock);
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ret = avs_hda_load_basefw(adev, fw);
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spin_lock(&bus->reg_lock);
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snd_hdac_stream_stop(hdac_stream(host_stream));
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spin_unlock(&bus->reg_lock);
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snd_hdac_dsp_cleanup(hdac_stream(host_stream), &dmab);
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release_stream:
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snd_hdac_ext_stream_release(host_stream, HDAC_EXT_STREAM_TYPE_HOST);
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snd_hdac_chip_updateb(bus, VS_LTRP, AZX_REG_VS_LTRP_GB_MASK, ltrp_gb);
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return ret;
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}
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const struct avs_dsp_ops avs_icl_dsp_ops = {
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const struct avs_dsp_ops avs_icl_dsp_ops = {
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.power = avs_dsp_core_power,
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.power = avs_dsp_core_power,
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.reset = avs_dsp_core_reset,
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.reset = avs_dsp_core_reset,
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@ -125,7 +185,7 @@ const struct avs_dsp_ops avs_icl_dsp_ops = {
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.irq_handler = avs_irq_handler,
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.irq_handler = avs_irq_handler,
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.irq_thread = avs_cnl_irq_thread,
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.irq_thread = avs_cnl_irq_thread,
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.int_control = avs_dsp_interrupt_control,
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.int_control = avs_dsp_interrupt_control,
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.load_basefw = avs_hda_load_basefw,
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.load_basefw = avs_icl_load_basefw,
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.load_lib = avs_hda_load_library,
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.load_lib = avs_hda_load_library,
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.transfer_mods = avs_hda_transfer_modules,
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.transfer_mods = avs_hda_transfer_modules,
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.log_buffer_offset = avs_icl_log_buffer_offset,
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.log_buffer_offset = avs_icl_log_buffer_offset,
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@ -42,7 +42,7 @@ const struct avs_dsp_ops avs_tgl_dsp_ops = {
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.irq_handler = avs_irq_handler,
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.irq_handler = avs_irq_handler,
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.irq_thread = avs_cnl_irq_thread,
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.irq_thread = avs_cnl_irq_thread,
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.int_control = avs_dsp_interrupt_control,
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.int_control = avs_dsp_interrupt_control,
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.load_basefw = avs_hda_load_basefw,
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.load_basefw = avs_icl_load_basefw,
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.load_lib = avs_hda_load_library,
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.load_lib = avs_hda_load_library,
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.transfer_mods = avs_hda_transfer_modules,
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.transfer_mods = avs_hda_transfer_modules,
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.log_buffer_offset = avs_icl_log_buffer_offset,
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.log_buffer_offset = avs_icl_log_buffer_offset,
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