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i3c: mipi-i3c-hci: Resume controller explicitly

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On an HW I'm using in enabling work the RESUME bit is not set in the
HC_CONTROLLER register when Host Controller goes to halt state. Value 1
should mean controller is suspended when reading and writing 1 resumes it.

Because of this erratic behaviour plain HC_CONTROL read and write back
won't resume the controller. Therefore do it by setting the RESUME bit
explicitly.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20230921055704.1087277-12-jarkko.nikula@linux.intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Jarkko Nikula 2023-09-21 08:57:03 +03:00 committed by Alexandre Belloni
parent 4c36f656b7
commit 3521fa63c1
1 changed files with 1 additions and 2 deletions
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3
drivers/i3c/master/mipi-i3c-hci/core.c
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@ -174,8 +174,7 @@ static void i3c_hci_bus_cleanup(struct i3c_master_controller *m)
void mipi_i3c_hci_resume(struct i3c_hci *hci)
{
/* the HC_CONTROL_RESUME bit is R/W1C so just read and write back */
reg_write(HC_CONTROL, reg_read(HC_CONTROL));
reg_set(HC_CONTROL, HC_CONTROL_RESUME);
}
/* located here rather than pio.c because needed bits are in core reg space */