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net/ucc_geth: update riscTx and riscRx in ucc_geth

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Change the definition of riscTx and riscRx to unsigned integer instead of
enum, and change their values to support 4 risc allocation if the qe has
4 RISC engines.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Haiying Wang 2009-04-29 14:14:35 -04:00 committed by Kumar Gala
parent 06c4435021
commit 345f84227b
2 changed files with 13 additions and 5 deletions
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14
drivers/net/ucc_geth.c
View file

@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
u8 num_entries,
u32 thread_size,
u32 thread_alignment,
enum qe_risc_allocation risc,
unsigned int risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
static int return_init_enet_entries(struct ucc_geth_private *ugeth,
u32 *p_start,
u8 num_entries,
enum qe_risc_allocation risc,
unsigned int risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
u32 __iomem *p_start,
u8 num_entries,
u32 thread_size,
enum qe_risc_allocation risc,
unsigned int risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@ -2135,6 +2135,14 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth)
return -ENOMEM;
}
/* read the number of risc engines, update the riscTx and riscRx
* if there are 4 riscs in QE
*/
if (qe_get_num_of_risc() == 4) {
ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
}
ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
if (!ugeth->ug_regs) {
if (netif_msg_probe(ugeth))

4
drivers/net/ucc_geth.h
View file

@ -1120,8 +1120,8 @@ struct ucc_geth_info {
enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
enum ucc_geth_num_of_threads numThreadsTx;
enum ucc_geth_num_of_threads numThreadsRx;
enum qe_risc_allocation riscTx;
enum qe_risc_allocation riscRx;
unsigned int riscTx;
unsigned int riscRx;
};
/* structure representing UCC GETH */