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drm/i915: Move BXT pll configuration logic to intel_dpll_mgr.c
Move the code for configurating BXT plls into the shared dpll code, so that the platform specific details are hidden behind that interface. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-12-git-send-email-ander.conselvan.de.oliveira@intel.com
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304b65cbdc
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34177c249a
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@ -1025,151 +1025,12 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
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return true;
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return true;
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}
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}
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/* bxt clock parameters */
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struct bxt_clk_div {
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int clock;
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uint32_t p1;
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uint32_t p2;
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uint32_t m2_int;
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uint32_t m2_frac;
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bool m2_frac_en;
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uint32_t n;
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};
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/* pre-calculated values for DP linkrates */
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static const struct bxt_clk_div bxt_dp_clk_val[] = {
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{162000, 4, 2, 32, 1677722, 1, 1},
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{270000, 4, 1, 27, 0, 0, 1},
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{540000, 2, 1, 27, 0, 0, 1},
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{216000, 3, 2, 32, 1677722, 1, 1},
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{243000, 4, 1, 24, 1258291, 1, 1},
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{324000, 4, 1, 32, 1677722, 1, 1},
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{432000, 3, 1, 32, 1677722, 1, 1}
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};
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static bool
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static bool
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bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
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bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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struct intel_crtc_state *crtc_state,
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struct intel_encoder *intel_encoder)
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struct intel_encoder *intel_encoder)
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{
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{
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struct intel_shared_dpll *pll;
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return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
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struct bxt_clk_div clk_div = {0};
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int vco = 0;
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uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
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uint32_t lanestagger;
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int clock = crtc_state->port_clock;
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if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
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intel_clock_t best_clock;
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/* Calculate HDMI div */
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/*
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* FIXME: tie the following calculation into
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* i9xx_crtc_compute_clock
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*/
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if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
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DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
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clock, pipe_name(intel_crtc->pipe));
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return false;
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}
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clk_div.p1 = best_clock.p1;
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clk_div.p2 = best_clock.p2;
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WARN_ON(best_clock.m1 != 2);
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clk_div.n = best_clock.n;
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clk_div.m2_int = best_clock.m2 >> 22;
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clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
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clk_div.m2_frac_en = clk_div.m2_frac != 0;
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vco = best_clock.vco;
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} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
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intel_encoder->type == INTEL_OUTPUT_EDP) {
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int i;
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clk_div = bxt_dp_clk_val[0];
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for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
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if (bxt_dp_clk_val[i].clock == clock) {
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clk_div = bxt_dp_clk_val[i];
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break;
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}
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}
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vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
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}
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if (vco >= 6200000 && vco <= 6700000) {
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prop_coef = 4;
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int_coef = 9;
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gain_ctl = 3;
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targ_cnt = 8;
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} else if ((vco > 5400000 && vco < 6200000) ||
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(vco >= 4800000 && vco < 5400000)) {
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prop_coef = 5;
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int_coef = 11;
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gain_ctl = 3;
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targ_cnt = 9;
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} else if (vco == 5400000) {
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prop_coef = 3;
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int_coef = 8;
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gain_ctl = 1;
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targ_cnt = 9;
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} else {
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DRM_ERROR("Invalid VCO\n");
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return false;
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}
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (clock > 270000)
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lanestagger = 0x18;
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else if (clock > 135000)
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lanestagger = 0x0d;
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else if (clock > 67000)
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lanestagger = 0x07;
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else if (clock > 33000)
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lanestagger = 0x04;
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else
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lanestagger = 0x02;
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crtc_state->dpll_hw_state.ebb0 =
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PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
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crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
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crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
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crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
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if (clk_div.m2_frac_en)
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crtc_state->dpll_hw_state.pll3 =
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PORT_PLL_M2_FRAC_ENABLE;
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crtc_state->dpll_hw_state.pll6 =
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prop_coef | PORT_PLL_INT_COEFF(int_coef);
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crtc_state->dpll_hw_state.pll6 |=
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PORT_PLL_GAIN_CTL(gain_ctl);
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crtc_state->dpll_hw_state.pll8 = targ_cnt;
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crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
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crtc_state->dpll_hw_state.pll10 =
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PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
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| PORT_PLL_DCO_AMP_OVR_EN_H;
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crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
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crtc_state->dpll_hw_state.pcsdw12 =
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LANESTAGGER_STRAP_OVRD | lanestagger;
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pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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pipe_name(intel_crtc->pipe));
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return false;
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}
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/* shared DPLL id 0 is DPLL A */
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crtc_state->ddi_pll_sel = pll->id;
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return true;
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}
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}
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/*
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/*
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@ -1342,29 +1342,156 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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return ret;
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return ret;
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}
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}
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/* bxt clock parameters */
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struct bxt_clk_div {
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int clock;
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uint32_t p1;
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uint32_t p2;
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uint32_t m2_int;
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uint32_t m2_frac;
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bool m2_frac_en;
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uint32_t n;
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};
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/* pre-calculated values for DP linkrates */
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static const struct bxt_clk_div bxt_dp_clk_val[] = {
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{162000, 4, 2, 32, 1677722, 1, 1},
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{270000, 4, 1, 27, 0, 0, 1},
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{540000, 2, 1, 27, 0, 0, 1},
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{216000, 3, 2, 32, 1677722, 1, 1},
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{243000, 4, 1, 24, 1258291, 1, 1},
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{324000, 4, 1, 32, 1677722, 1, 1},
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{432000, 3, 1, 32, 1677722, 1, 1}
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};
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static struct intel_shared_dpll *
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static struct intel_shared_dpll *
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bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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struct intel_encoder *encoder)
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{
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_digital_port *intel_dig_port;
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struct intel_shared_dpll *pll;
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struct intel_shared_dpll *pll;
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enum intel_dpll_id i;
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enum intel_dpll_id i;
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struct intel_digital_port *intel_dig_port;
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struct bxt_clk_div clk_div = {0};
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int vco = 0;
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uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
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uint32_t lanestagger;
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int clock = crtc_state->port_clock;
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/* PLL is attached to port in bxt */
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if (encoder->type == INTEL_OUTPUT_HDMI) {
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encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
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intel_clock_t best_clock;
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if (WARN_ON(!encoder))
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/* Calculate HDMI div */
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/*
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* FIXME: tie the following calculation into
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* i9xx_crtc_compute_clock
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*/
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if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
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DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
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clock, pipe_name(crtc->pipe));
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return NULL;
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}
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clk_div.p1 = best_clock.p1;
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clk_div.p2 = best_clock.p2;
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WARN_ON(best_clock.m1 != 2);
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clk_div.n = best_clock.n;
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clk_div.m2_int = best_clock.m2 >> 22;
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clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
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clk_div.m2_frac_en = clk_div.m2_frac != 0;
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vco = best_clock.vco;
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} else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
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encoder->type == INTEL_OUTPUT_EDP) {
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int i;
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clk_div = bxt_dp_clk_val[0];
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for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
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if (bxt_dp_clk_val[i].clock == clock) {
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clk_div = bxt_dp_clk_val[i];
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break;
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}
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}
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vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
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}
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if (vco >= 6200000 && vco <= 6700000) {
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prop_coef = 4;
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int_coef = 9;
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gain_ctl = 3;
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targ_cnt = 8;
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} else if ((vco > 5400000 && vco < 6200000) ||
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(vco >= 4800000 && vco < 5400000)) {
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prop_coef = 5;
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int_coef = 11;
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gain_ctl = 3;
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targ_cnt = 9;
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} else if (vco == 5400000) {
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prop_coef = 3;
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int_coef = 8;
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gain_ctl = 1;
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targ_cnt = 9;
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} else {
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DRM_ERROR("Invalid VCO\n");
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return NULL;
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return NULL;
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}
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (clock > 270000)
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lanestagger = 0x18;
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else if (clock > 135000)
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lanestagger = 0x0d;
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else if (clock > 67000)
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lanestagger = 0x07;
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else if (clock > 33000)
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lanestagger = 0x04;
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else
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lanestagger = 0x02;
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crtc_state->dpll_hw_state.ebb0 =
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PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
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crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
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crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
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crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
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if (clk_div.m2_frac_en)
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crtc_state->dpll_hw_state.pll3 =
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PORT_PLL_M2_FRAC_ENABLE;
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crtc_state->dpll_hw_state.pll6 =
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prop_coef | PORT_PLL_INT_COEFF(int_coef);
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crtc_state->dpll_hw_state.pll6 |=
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PORT_PLL_GAIN_CTL(gain_ctl);
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crtc_state->dpll_hw_state.pll8 = targ_cnt;
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crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
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crtc_state->dpll_hw_state.pll10 =
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PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
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| PORT_PLL_DCO_AMP_OVR_EN_H;
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crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
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crtc_state->dpll_hw_state.pcsdw12 =
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LANESTAGGER_STRAP_OVRD | lanestagger;
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intel_dig_port = enc_to_dig_port(&encoder->base);
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intel_dig_port = enc_to_dig_port(&encoder->base);
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/* 1:1 mapping between ports and PLLs */
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/* 1:1 mapping between ports and PLLs */
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i = (enum intel_dpll_id)intel_dig_port->port;
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i = (enum intel_dpll_id) intel_dig_port->port;
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pll = &dev_priv->shared_dplls[i];
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pll = intel_get_shared_dpll_by_id(dev_priv, i);
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DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
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DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
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crtc->base.base.id, pll->name);
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crtc->base.base.id, pll->name);
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intel_reference_shared_dpll(pll, crtc_state);
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intel_reference_shared_dpll(pll, crtc_state);
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/* shared DPLL id 0 is DPLL A */
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crtc_state->ddi_pll_sel = pll->id;
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return pll;
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return pll;
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}
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}
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