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x86/CPU/AMD: Add ZenX generations flags
Add X86_FEATURE flags for each Zen generation. They should be used from now on instead of checking f/m/s. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lore.kernel.org/r/20231120104152.13740-2-bp@alien8.de
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@ -218,7 +218,7 @@
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#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU based on Zen microarchitecture */
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#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
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#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
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#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
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@ -312,6 +312,9 @@
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#define X86_FEATURE_SRSO_ALIAS (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
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#define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* "" Issue an IBPB only on VMEXIT */
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#define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
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#define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
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#define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
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#define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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@ -616,6 +616,49 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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}
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resctrl_cpu_detect(c);
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/* Figure out Zen generations: */
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switch (c->x86) {
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case 0x17: {
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switch (c->x86_model) {
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case 0x00 ... 0x2f:
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case 0x50 ... 0x5f:
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setup_force_cpu_cap(X86_FEATURE_ZEN);
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break;
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case 0x30 ... 0x4f:
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case 0x60 ... 0x7f:
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case 0x90 ... 0x91:
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case 0xa0 ... 0xaf:
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setup_force_cpu_cap(X86_FEATURE_ZEN2);
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break;
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default:
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goto warn;
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}
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break;
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}
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case 0x19: {
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switch (c->x86_model) {
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case 0x00 ... 0x0f:
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case 0x20 ... 0x5f:
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setup_force_cpu_cap(X86_FEATURE_ZEN3);
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break;
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case 0x10 ... 0x1f:
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case 0x60 ... 0xaf:
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setup_force_cpu_cap(X86_FEATURE_ZEN4);
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break;
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default:
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goto warn;
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}
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break;
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}
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default:
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break;
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}
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return;
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warn:
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WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
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}
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static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
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@ -974,8 +1017,6 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
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static void init_amd_zn(struct cpuinfo_x86 *c)
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{
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set_cpu_cap(c, X86_FEATURE_ZEN);
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#ifdef CONFIG_NUMA
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node_reclaim_distance = 32;
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#endif
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@ -1037,6 +1078,22 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
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}
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}
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static void init_amd_zen(struct cpuinfo_x86 *c)
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{
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}
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static void init_amd_zen2(struct cpuinfo_x86 *c)
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{
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}
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static void init_amd_zen3(struct cpuinfo_x86 *c)
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{
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}
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static void init_amd_zen4(struct cpuinfo_x86 *c)
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{
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}
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static void init_amd(struct cpuinfo_x86 *c)
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{
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u64 vm_cr;
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@ -1077,6 +1134,15 @@ static void init_amd(struct cpuinfo_x86 *c)
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case 0x19: init_amd_zn(c); break;
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}
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if (boot_cpu_has(X86_FEATURE_ZEN))
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init_amd_zen(c);
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else if (boot_cpu_has(X86_FEATURE_ZEN2))
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init_amd_zen2(c);
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else if (boot_cpu_has(X86_FEATURE_ZEN3))
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init_amd_zen3(c);
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else if (boot_cpu_has(X86_FEATURE_ZEN4))
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init_amd_zen4(c);
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/*
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* Enable workaround for FXSAVE leak on CPUs
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* without a XSaveErPtr feature
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