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drm/radeon/dpm: Clean up errors in sumo_dpm.c

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Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that close parenthesis ')'
ERROR: spaces required around that '?' (ctx:VxW)

Signed-off-by: GuoHua Chen <chenguohua_716@163.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
GuoHua Chen 2024-01-11 07:44:30 +00:00 committed by Alex Deucher
parent 765290661c
commit 30d30e0f15
1 changed files with 8 additions and 10 deletions
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18
drivers/gpu/drm/radeon/sumo_dpm.c
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@ -33,8 +33,7 @@
#define SUMO_MINIMUM_ENGINE_CLOCK 800 #define SUMO_MINIMUM_ENGINE_CLOCK 800
#define BOOST_DPM_LEVEL 7 #define BOOST_DPM_LEVEL 7
static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = {
{
SUMO_UTC_DFLT_00, SUMO_UTC_DFLT_00,
SUMO_UTC_DFLT_01, SUMO_UTC_DFLT_01,
SUMO_UTC_DFLT_02, SUMO_UTC_DFLT_02,
@ -52,8 +51,7 @@ static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
SUMO_UTC_DFLT_14, SUMO_UTC_DFLT_14,
}; };
static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = {
{
SUMO_DTC_DFLT_00, SUMO_DTC_DFLT_00,
SUMO_DTC_DFLT_01, SUMO_DTC_DFLT_01,
SUMO_DTC_DFLT_02, SUMO_DTC_DFLT_02,
@ -109,11 +107,11 @@ static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
local1 = RREG32(CG_CGTT_LOCAL_1); local1 = RREG32(CG_CGTT_LOCAL_1);
if (enable) { if (enable) {
WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK));
WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK));
} else { } else {
WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK));
WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK));
} }
} }
@ -702,9 +700,9 @@ static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
u32 nbps1_new = 0; u32 nbps1_new = 0;
if (old_ps != NULL) if (old_ps != NULL)
nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
if (nbps1_old == 0 && nbps1_new == 1) if (nbps1_old == 0 && nbps1_new == 1)
sumo_smu_notify_alt_vddnb_change(rdev, 1, 1); sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);