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mfd: bd71837: Core driver for ROHM BD71837 PMIC
ROHM BD71837 PMIC MFD driver providing interrupts and support for three subsystems: - clk - Regulators - input/power-key Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Matti Vaittinen
Lee Jones
parent
f863ae594d
commit
30107fa690
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@ -1817,6 +1817,19 @@ config MFD_STW481X
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in various ST Microelectronics and ST-Ericsson embedded
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Nomadik series.
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config MFD_ROHM_BD718XX
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tristate "ROHM BD71837 Power Management IC"
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depends on I2C=y
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depends on OF
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select REGMAP_I2C
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select REGMAP_IRQ
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select MFD_CORE
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help
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Select this option to get support for the ROHM BD71837
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Power Management ICs. BD71837 is designed to power processors like
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NXP i.MX8. It contains 8 BUCK outputs and 7 LDOs, voltage monitoring
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and emergency shut down as well as 32,768KHz clock output.
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config MFD_STM32_LPTIMER
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tristate "Support for STM32 Low-Power Timer"
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depends on (ARCH_STM32 && OF) || COMPILE_TEST
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@ -239,4 +239,5 @@ obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o
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obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o
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obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o
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obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o
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obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o
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211
drivers/mfd/rohm-bd718x7.c
Normal file
211
drivers/mfd/rohm-bd718x7.c
Normal file
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@ -0,0 +1,211 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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//
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// Copyright (C) 2018 ROHM Semiconductors
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//
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// ROHM BD71837MWV PMIC driver
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//
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// Datasheet available from
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// https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e
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#include <linux/i2c.h>
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#include <linux/input.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/rohm-bd718x7.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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/*
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* gpio_keys.h requires definiton of bool. It is brought in
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* by above includes. Keep this as last until gpio_keys.h gets fixed.
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*/
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#include <linux/gpio_keys.h>
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static const u8 supported_revisions[] = { 0xA2 /* BD71837 */ };
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static struct gpio_keys_button button = {
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.code = KEY_POWER,
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.gpio = -1,
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.type = EV_KEY,
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};
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static struct gpio_keys_platform_data bd718xx_powerkey_data = {
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.buttons = &button,
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.nbuttons = 1,
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.name = "bd718xx-pwrkey",
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};
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static struct mfd_cell bd71837_mfd_cells[] = {
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{
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.name = "gpio-keys",
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.platform_data = &bd718xx_powerkey_data,
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.pdata_size = sizeof(bd718xx_powerkey_data),
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},
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{ .name = "bd71837-clk", },
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{ .name = "bd71837-pmic", },
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};
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static const struct regmap_irq bd71837_irqs[] = {
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REGMAP_IRQ_REG(BD71837_INT_SWRST, 0, BD71837_INT_SWRST_MASK),
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REGMAP_IRQ_REG(BD71837_INT_PWRBTN_S, 0, BD71837_INT_PWRBTN_S_MASK),
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REGMAP_IRQ_REG(BD71837_INT_PWRBTN_L, 0, BD71837_INT_PWRBTN_L_MASK),
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REGMAP_IRQ_REG(BD71837_INT_PWRBTN, 0, BD71837_INT_PWRBTN_MASK),
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REGMAP_IRQ_REG(BD71837_INT_WDOG, 0, BD71837_INT_WDOG_MASK),
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REGMAP_IRQ_REG(BD71837_INT_ON_REQ, 0, BD71837_INT_ON_REQ_MASK),
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REGMAP_IRQ_REG(BD71837_INT_STBY_REQ, 0, BD71837_INT_STBY_REQ_MASK),
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};
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static struct regmap_irq_chip bd71837_irq_chip = {
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.name = "bd71837-irq",
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.irqs = bd71837_irqs,
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.num_irqs = ARRAY_SIZE(bd71837_irqs),
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.num_regs = 1,
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.irq_reg_stride = 1,
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.status_base = BD71837_REG_IRQ,
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.mask_base = BD71837_REG_MIRQ,
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.ack_base = BD71837_REG_IRQ,
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.init_ack_masked = true,
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.mask_invert = false,
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};
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static const struct regmap_range pmic_status_range = {
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.range_min = BD71837_REG_IRQ,
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.range_max = BD71837_REG_POW_STATE,
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};
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static const struct regmap_access_table volatile_regs = {
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.yes_ranges = &pmic_status_range,
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.n_yes_ranges = 1,
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};
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static const struct regmap_config bd71837_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.volatile_table = &volatile_regs,
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.max_register = BD71837_MAX_REGISTER - 1,
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.cache_type = REGCACHE_RBTREE,
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};
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static int bd71837_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct bd71837 *bd71837;
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int ret, i;
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unsigned int val;
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bd71837 = devm_kzalloc(&i2c->dev, sizeof(struct bd71837), GFP_KERNEL);
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if (!bd71837)
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return -ENOMEM;
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bd71837->chip_irq = i2c->irq;
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if (!bd71837->chip_irq) {
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dev_err(&i2c->dev, "No IRQ configured\n");
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return -EINVAL;
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}
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bd71837->dev = &i2c->dev;
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dev_set_drvdata(&i2c->dev, bd71837);
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bd71837->regmap = devm_regmap_init_i2c(i2c, &bd71837_regmap_config);
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if (IS_ERR(bd71837->regmap)) {
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dev_err(&i2c->dev, "regmap initialization failed\n");
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return PTR_ERR(bd71837->regmap);
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}
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ret = regmap_read(bd71837->regmap, BD71837_REG_REV, &val);
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if (ret) {
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dev_err(&i2c->dev, "Read BD71837_REG_DEVICE failed\n");
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return ret;
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}
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for (i = 0; i < ARRAY_SIZE(supported_revisions); i++)
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if (supported_revisions[i] == val)
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break;
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if (i == ARRAY_SIZE(supported_revisions)) {
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dev_err(&i2c->dev, "Unsupported chip revision\n");
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return -ENODEV;
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}
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ret = devm_regmap_add_irq_chip(&i2c->dev, bd71837->regmap,
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bd71837->chip_irq, IRQF_ONESHOT, 0,
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&bd71837_irq_chip, &bd71837->irq_data);
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if (ret) {
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dev_err(&i2c->dev, "Failed to add irq_chip\n");
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return ret;
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}
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/* Configure short press to 10 milliseconds */
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ret = regmap_update_bits(bd71837->regmap,
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BD71837_REG_PWRONCONFIG0,
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BD718XX_PWRBTN_PRESS_DURATION_MASK,
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BD718XX_PWRBTN_SHORT_PRESS_10MS);
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if (ret) {
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dev_err(&i2c->dev,
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"Failed to configure button short press timeout\n");
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return ret;
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}
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/* Configure long press to 10 seconds */
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ret = regmap_update_bits(bd71837->regmap,
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BD71837_REG_PWRONCONFIG1,
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BD718XX_PWRBTN_PRESS_DURATION_MASK,
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BD718XX_PWRBTN_LONG_PRESS_10S);
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if (ret) {
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dev_err(&i2c->dev,
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"Failed to configure button long press timeout\n");
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return ret;
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}
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ret = regmap_irq_get_virq(bd71837->irq_data, BD71837_INT_PWRBTN_S);
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if (ret < 0) {
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dev_err(&i2c->dev, "Failed to get the IRQ\n");
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return ret;
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}
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button.irq = ret;
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ret = devm_mfd_add_devices(bd71837->dev, PLATFORM_DEVID_AUTO,
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bd71837_mfd_cells,
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ARRAY_SIZE(bd71837_mfd_cells), NULL, 0,
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regmap_irq_get_domain(bd71837->irq_data));
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if (ret)
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dev_err(&i2c->dev, "Failed to create subdevices\n");
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return ret;
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}
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static const struct of_device_id bd71837_of_match[] = {
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{ .compatible = "rohm,bd71837", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, bd71837_of_match);
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static struct i2c_driver bd71837_i2c_driver = {
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.driver = {
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.name = "rohm-bd718x7",
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.of_match_table = bd71837_of_match,
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},
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.probe = bd71837_i2c_probe,
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};
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static int __init bd71837_i2c_init(void)
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{
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return i2c_add_driver(&bd71837_i2c_driver);
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}
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/* Initialise early so consumer devices can complete system boot */
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subsys_initcall(bd71837_i2c_init);
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static void __exit bd71837_i2c_exit(void)
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{
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i2c_del_driver(&bd71837_i2c_driver);
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}
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module_exit(bd71837_i2c_exit);
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MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
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MODULE_DESCRIPTION("ROHM BD71837 Power Management IC driver");
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MODULE_LICENSE("GPL");
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332
include/linux/mfd/rohm-bd718x7.h
Normal file
332
include/linux/mfd/rohm-bd718x7.h
Normal file
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@ -0,0 +1,332 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2018 ROHM Semiconductors */
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#ifndef __LINUX_MFD_BD71837_H__
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#define __LINUX_MFD_BD71837_H__
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#include <linux/regmap.h>
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enum {
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BD71837_BUCK1 = 0,
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BD71837_BUCK2,
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BD71837_BUCK3,
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BD71837_BUCK4,
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BD71837_BUCK5,
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BD71837_BUCK6,
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BD71837_BUCK7,
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BD71837_BUCK8,
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BD71837_LDO1,
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BD71837_LDO2,
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BD71837_LDO3,
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BD71837_LDO4,
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BD71837_LDO5,
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BD71837_LDO6,
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BD71837_LDO7,
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BD71837_REGULATOR_CNT,
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};
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#define BD71837_BUCK1_VOLTAGE_NUM 0x40
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#define BD71837_BUCK2_VOLTAGE_NUM 0x40
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#define BD71837_BUCK3_VOLTAGE_NUM 0x40
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#define BD71837_BUCK4_VOLTAGE_NUM 0x40
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#define BD71837_BUCK5_VOLTAGE_NUM 0x08
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#define BD71837_BUCK6_VOLTAGE_NUM 0x04
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#define BD71837_BUCK7_VOLTAGE_NUM 0x08
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#define BD71837_BUCK8_VOLTAGE_NUM 0x40
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#define BD71837_LDO1_VOLTAGE_NUM 0x04
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#define BD71837_LDO2_VOLTAGE_NUM 0x02
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#define BD71837_LDO3_VOLTAGE_NUM 0x10
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#define BD71837_LDO4_VOLTAGE_NUM 0x10
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#define BD71837_LDO5_VOLTAGE_NUM 0x10
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#define BD71837_LDO6_VOLTAGE_NUM 0x10
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#define BD71837_LDO7_VOLTAGE_NUM 0x10
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enum {
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BD71837_REG_REV = 0x00,
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BD71837_REG_SWRESET = 0x01,
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BD71837_REG_I2C_DEV = 0x02,
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BD71837_REG_PWRCTRL0 = 0x03,
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BD71837_REG_PWRCTRL1 = 0x04,
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BD71837_REG_BUCK1_CTRL = 0x05,
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BD71837_REG_BUCK2_CTRL = 0x06,
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK5_CTRL = 0x09,
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BD71837_REG_BUCK6_CTRL = 0x0A,
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BD71837_REG_BUCK7_CTRL = 0x0B,
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BD71837_REG_BUCK8_CTRL = 0x0C,
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BD71837_REG_BUCK1_VOLT_RUN = 0x0D,
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BD71837_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD71837_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD71837_REG_BUCK2_VOLT_RUN = 0x10,
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BD71837_REG_BUCK2_VOLT_IDLE = 0x11,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_BUCK5_VOLT = 0x14,
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BD71837_REG_BUCK6_VOLT = 0x15,
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BD71837_REG_BUCK7_VOLT = 0x16,
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BD71837_REG_BUCK8_VOLT = 0x17,
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BD71837_REG_LDO1_VOLT = 0x18,
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BD71837_REG_LDO2_VOLT = 0x19,
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BD71837_REG_LDO3_VOLT = 0x1A,
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BD71837_REG_LDO4_VOLT = 0x1B,
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BD71837_REG_LDO5_VOLT = 0x1C,
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BD71837_REG_LDO6_VOLT = 0x1D,
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BD71837_REG_LDO7_VOLT = 0x1E,
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BD71837_REG_TRANS_COND0 = 0x1F,
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BD71837_REG_TRANS_COND1 = 0x20,
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BD71837_REG_VRFAULTEN = 0x21,
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BD71837_REG_MVRFLTMASK0 = 0x22,
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BD71837_REG_MVRFLTMASK1 = 0x23,
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BD71837_REG_MVRFLTMASK2 = 0x24,
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BD71837_REG_RCVCFG = 0x25,
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BD71837_REG_RCVNUM = 0x26,
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BD71837_REG_PWRONCONFIG0 = 0x27,
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BD71837_REG_PWRONCONFIG1 = 0x28,
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BD71837_REG_RESETSRC = 0x29,
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BD71837_REG_MIRQ = 0x2A,
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BD71837_REG_IRQ = 0x2B,
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BD71837_REG_IN_MON = 0x2C,
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BD71837_REG_POW_STATE = 0x2D,
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BD71837_REG_OUT32K = 0x2E,
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BD71837_REG_REGLOCK = 0x2F,
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BD71837_REG_OTPVER = 0xFF,
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BD71837_MAX_REGISTER = 0x100,
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};
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#define REGLOCK_PWRSEQ 0x1
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#define REGLOCK_VREG 0x10
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/* Generic BUCK control masks */
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#define BD71837_BUCK_SEL 0x02
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#define BD71837_BUCK_EN 0x01
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#define BD71837_BUCK_RUN_ON 0x04
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/* Generic LDO masks */
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#define BD71837_LDO_SEL 0x80
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#define BD71837_LDO_EN 0x40
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/* BD71837 BUCK ramp rate CTRL reg bits */
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#define BUCK_RAMPRATE_MASK 0xC0
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#define BUCK_RAMPRATE_10P00MV 0x0
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#define BUCK_RAMPRATE_5P00MV 0x1
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#define BUCK_RAMPRATE_2P50MV 0x2
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#define BUCK_RAMPRATE_1P25MV 0x3
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/* BD71837_REG_BUCK1_VOLT_RUN bits */
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#define BUCK1_RUN_MASK 0x3F
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#define BUCK1_RUN_DEFAULT 0x14
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/* BD71837_REG_BUCK1_VOLT_SUSP bits */
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#define BUCK1_SUSP_MASK 0x3F
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#define BUCK1_SUSP_DEFAULT 0x14
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/* BD71837_REG_BUCK1_VOLT_IDLE bits */
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#define BUCK1_IDLE_MASK 0x3F
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#define BUCK1_IDLE_DEFAULT 0x14
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/* BD71837_REG_BUCK2_VOLT_RUN bits */
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#define BUCK2_RUN_MASK 0x3F
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#define BUCK2_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK2_VOLT_IDLE bits */
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#define BUCK2_IDLE_MASK 0x3F
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#define BUCK2_IDLE_DEFAULT 0x14
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/* BD71837_REG_BUCK3_VOLT_RUN bits */
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#define BUCK3_RUN_MASK 0x3F
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#define BUCK3_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK4_VOLT_RUN bits */
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#define BUCK4_RUN_MASK 0x3F
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#define BUCK4_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK5_VOLT bits */
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#define BUCK5_MASK 0x07
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#define BUCK5_DEFAULT 0x02
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/* BD71837_REG_BUCK6_VOLT bits */
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#define BUCK6_MASK 0x03
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#define BUCK6_DEFAULT 0x03
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/* BD71837_REG_BUCK7_VOLT bits */
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#define BUCK7_MASK 0x07
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#define BUCK7_DEFAULT 0x03
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/* BD71837_REG_BUCK8_VOLT bits */
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#define BUCK8_MASK 0x3F
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#define BUCK8_DEFAULT 0x1E
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|
||||
/* BD71837_REG_IRQ bits */
|
||||
#define IRQ_SWRST 0x40
|
||||
#define IRQ_PWRON_S 0x20
|
||||
#define IRQ_PWRON_L 0x10
|
||||
#define IRQ_PWRON 0x08
|
||||
#define IRQ_WDOG 0x04
|
||||
#define IRQ_ON_REQ 0x02
|
||||
#define IRQ_STBY_REQ 0x01
|
||||
|
||||
/* BD71837_REG_OUT32K bits */
|
||||
#define BD71837_OUT32K_EN 0x01
|
||||
|
||||
/* BD71837 gated clock rate */
|
||||
#define BD71837_CLK_RATE 32768
|
||||
|
||||
/* ROHM BD71837 irqs */
|
||||
enum {
|
||||
BD71837_INT_STBY_REQ,
|
||||
BD71837_INT_ON_REQ,
|
||||
BD71837_INT_WDOG,
|
||||
BD71837_INT_PWRBTN,
|
||||
BD71837_INT_PWRBTN_L,
|
||||
BD71837_INT_PWRBTN_S,
|
||||
BD71837_INT_SWRST
|
||||
};
|
||||
|
||||
/* ROHM BD71837 interrupt masks */
|
||||
#define BD71837_INT_SWRST_MASK 0x40
|
||||
#define BD71837_INT_PWRBTN_S_MASK 0x20
|
||||
#define BD71837_INT_PWRBTN_L_MASK 0x10
|
||||
#define BD71837_INT_PWRBTN_MASK 0x8
|
||||
#define BD71837_INT_WDOG_MASK 0x4
|
||||
#define BD71837_INT_ON_REQ_MASK 0x2
|
||||
#define BD71837_INT_STBY_REQ_MASK 0x1
|
||||
|
||||
/* BD71837_REG_LDO1_VOLT bits */
|
||||
#define LDO1_MASK 0x03
|
||||
|
||||
/* BD71837_REG_LDO1_VOLT bits */
|
||||
#define LDO2_MASK 0x20
|
||||
|
||||
/* BD71837_REG_LDO3_VOLT bits */
|
||||
#define LDO3_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO4_VOLT bits */
|
||||
#define LDO4_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO5_VOLT bits */
|
||||
#define LDO5_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO6_VOLT bits */
|
||||
#define LDO6_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO7_VOLT bits */
|
||||
#define LDO7_MASK 0x0F
|
||||
|
||||
/* Register write induced reset settings */
|
||||
|
||||
/*
|
||||
* Even though the bit zero is not SWRESET type we still want to write zero
|
||||
* to it when changing type. Bit zero is 'SWRESET' trigger bit and if we
|
||||
* write 1 to it we will trigger the action. So always write 0 to it when
|
||||
* changning SWRESET action - no matter what we read from it.
|
||||
*/
|
||||
#define BD71837_SWRESET_TYPE_MASK 7
|
||||
#define BD71837_SWRESET_TYPE_DISABLED 0
|
||||
#define BD71837_SWRESET_TYPE_COLD 4
|
||||
#define BD71837_SWRESET_TYPE_WARM 6
|
||||
|
||||
#define BD71837_SWRESET_RESET_MASK 1
|
||||
#define BD71837_SWRESET_RESET 1
|
||||
|
||||
/* Poweroff state transition conditions */
|
||||
|
||||
#define BD718XX_ON_REQ_POWEROFF_MASK 1
|
||||
#define BD718XX_SWRESET_POWEROFF_MASK 2
|
||||
#define BD718XX_WDOG_POWEROFF_MASK 4
|
||||
#define BD718XX_KEY_L_POWEROFF_MASK 8
|
||||
|
||||
#define BD718XX_POWOFF_TO_SNVS 0
|
||||
#define BD718XX_POWOFF_TO_RDY 0xF
|
||||
|
||||
#define BD718XX_POWOFF_TIME_MASK 0xF0
|
||||
enum {
|
||||
BD718XX_POWOFF_TIME_5MS = 0,
|
||||
BD718XX_POWOFF_TIME_10MS,
|
||||
BD718XX_POWOFF_TIME_15MS,
|
||||
BD718XX_POWOFF_TIME_20MS,
|
||||
BD718XX_POWOFF_TIME_25MS,
|
||||
BD718XX_POWOFF_TIME_30MS,
|
||||
BD718XX_POWOFF_TIME_35MS,
|
||||
BD718XX_POWOFF_TIME_40MS,
|
||||
BD718XX_POWOFF_TIME_45MS,
|
||||
BD718XX_POWOFF_TIME_50MS,
|
||||
BD718XX_POWOFF_TIME_75MS,
|
||||
BD718XX_POWOFF_TIME_100MS,
|
||||
BD718XX_POWOFF_TIME_250MS,
|
||||
BD718XX_POWOFF_TIME_500MS,
|
||||
BD718XX_POWOFF_TIME_750MS,
|
||||
BD718XX_POWOFF_TIME_1500MS
|
||||
};
|
||||
|
||||
/* Poweron sequence state transition conditions */
|
||||
#define BD718XX_RDY_TO_SNVS_MASK 0xF
|
||||
#define BD718XX_SNVS_TO_RUN_MASK 0xF0
|
||||
|
||||
#define BD718XX_PWR_TRIG_KEY_L 1
|
||||
#define BD718XX_PWR_TRIG_KEY_S 2
|
||||
#define BD718XX_PWR_TRIG_PMIC_ON 4
|
||||
#define BD718XX_PWR_TRIG_VSYS_UVLO 8
|
||||
#define BD718XX_RDY_TO_SNVS_SIFT 0
|
||||
#define BD718XX_SNVS_TO_RUN_SIFT 4
|
||||
|
||||
#define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF
|
||||
|
||||
/* Timeout value for detecting short press */
|
||||
enum {
|
||||
BD718XX_PWRBTN_SHORT_PRESS_10MS = 0,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_1000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_1500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_2000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_2500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_3000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_3500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_4000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_4500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_5000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_5500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_6000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_6500MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_7000MS,
|
||||
BD718XX_PWRBTN_SHORT_PRESS_7500MS
|
||||
};
|
||||
|
||||
/* Timeout value for detecting LONG press */
|
||||
enum {
|
||||
BD718XX_PWRBTN_LONG_PRESS_10MS = 0,
|
||||
BD718XX_PWRBTN_LONG_PRESS_1S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_2S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_3S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_4S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_5S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_6S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_7S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_8S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_9S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_10S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_11S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_12S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_13S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_14S,
|
||||
BD718XX_PWRBTN_LONG_PRESS_15S
|
||||
};
|
||||
|
||||
struct bd71837_pmic;
|
||||
struct bd71837_clk;
|
||||
|
||||
struct bd71837 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
unsigned long int id;
|
||||
|
||||
int chip_irq;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
|
||||
struct bd71837_pmic *pmic;
|
||||
struct bd71837_clk *clk;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_BD71837_H__ */
|
||||
Loading…
Reference in a new issue