mirror of
https://github.com/torvalds/linux
synced 2024-09-28 23:41:21 +00:00
drm/gma500: Add generic pipe/crtc functions
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson
parent
f0e9d89b9b
commit
2eff0b3359
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@ -24,6 +24,7 @@
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_drv.h"
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#include "framebuffer.h"
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/**
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* Returns whether any output on the specified pipe is of the specified type
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@ -46,6 +47,331 @@ bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
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return false;
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}
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void gma_wait_for_vblank(struct drm_device *dev)
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{
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/* Wait for 20ms, i.e. one cycle at 50hz. */
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mdelay(20);
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}
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int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
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int pipe = psb_intel_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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unsigned long start, offset;
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u32 dspcntr;
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int ret = 0;
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if (!gma_power_begin(dev, true))
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return 0;
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/* no fb bound */
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if (!crtc->fb) {
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dev_err(dev->dev, "No FB bound\n");
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goto gma_pipe_cleaner;
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}
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/* We are displaying this buffer, make sure it is actually loaded
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into the GTT */
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ret = psb_gtt_pin(psbfb->gtt);
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if (ret < 0)
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goto gma_pipe_set_base_exit;
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start = psbfb->gtt->offset;
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offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
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REG_WRITE(map->stride, crtc->fb->pitches[0]);
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dspcntr = REG_READ(map->cntr);
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dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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dspcntr |= DISPPLANE_8BPP;
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break;
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case 16:
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if (crtc->fb->depth == 15)
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dspcntr |= DISPPLANE_15_16BPP;
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else
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dspcntr |= DISPPLANE_16BPP;
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break;
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case 24:
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case 32:
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dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
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break;
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default:
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dev_err(dev->dev, "Unknown color depth\n");
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ret = -EINVAL;
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goto gma_pipe_set_base_exit;
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}
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REG_WRITE(map->cntr, dspcntr);
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dev_dbg(dev->dev,
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"Writing base %08lX %08lX %d %d\n", start, offset, x, y);
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/* FIXME: Investigate whether this really is the base for psb and why
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the linear offset is named base for the other chips. map->surf
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should be the base and map->linoff the offset for all chips */
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if (IS_PSB(dev)) {
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REG_WRITE(map->base, offset + start);
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REG_READ(map->base);
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} else {
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REG_WRITE(map->base, offset);
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REG_READ(map->base);
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REG_WRITE(map->surf, start);
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REG_READ(map->surf);
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}
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gma_pipe_cleaner:
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/* If there was a previous display we can now unpin it */
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if (old_fb)
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psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
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gma_pipe_set_base_exit:
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gma_power_end(dev);
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return ret;
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}
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/* Loads the palette/gamma unit for the CRTC with the prepared values */
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void gma_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
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int palreg = map->palette;
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int i;
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/* The clocks have to be on to load the palette. */
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if (!crtc->enabled)
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return;
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if (gma_power_begin(dev, false)) {
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for (i = 0; i < 256; i++) {
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REG_WRITE(palreg + 4 * i,
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((psb_intel_crtc->lut_r[i] +
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psb_intel_crtc->lut_adj[i]) << 16) |
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((psb_intel_crtc->lut_g[i] +
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psb_intel_crtc->lut_adj[i]) << 8) |
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(psb_intel_crtc->lut_b[i] +
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psb_intel_crtc->lut_adj[i]));
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}
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gma_power_end(dev);
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} else {
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for (i = 0; i < 256; i++) {
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/* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
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dev_priv->regs.pipe[0].palette[i] =
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((psb_intel_crtc->lut_r[i] +
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psb_intel_crtc->lut_adj[i]) << 16) |
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((psb_intel_crtc->lut_g[i] +
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psb_intel_crtc->lut_adj[i]) << 8) |
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(psb_intel_crtc->lut_b[i] +
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psb_intel_crtc->lut_adj[i]);
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}
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}
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}
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void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
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u32 start, u32 size)
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{
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int i;
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int end = (start + size > 256) ? 256 : start + size;
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for (i = start; i < end; i++) {
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psb_intel_crtc->lut_r[i] = red[i] >> 8;
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psb_intel_crtc->lut_g[i] = green[i] >> 8;
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psb_intel_crtc->lut_b[i] = blue[i] >> 8;
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}
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gma_crtc_load_lut(crtc);
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}
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/**
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* Sets the power management mode of the pipe and plane.
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*
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* This code should probably grow support for turning the cursor off and back
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* on appropriately at the same time as we're turning the pipe off/on.
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*/
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void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_intel_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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u32 temp;
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/* XXX: When our outputs are all unaware of DPMS modes other than off
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* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
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*/
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/* FIXME: Uncomment this when we move cdv to generic dpms
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if (IS_CDV(dev))
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cdv_intel_disable_self_refresh(dev);
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*/
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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if (psb_intel_crtc->active)
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break;
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psb_intel_crtc->active = true;
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/* Enable the DPLL */
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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REG_WRITE(map->dpll, temp);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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}
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/* Enable the plane */
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temp = REG_READ(map->cntr);
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if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
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REG_WRITE(map->cntr,
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temp | DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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REG_WRITE(map->base, REG_READ(map->base));
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}
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udelay(150);
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/* Enable the pipe */
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temp = REG_READ(map->conf);
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if ((temp & PIPEACONF_ENABLE) == 0)
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REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
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temp = REG_READ(map->status);
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temp &= ~(0xFFFF);
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temp |= PIPE_FIFO_UNDERRUN;
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REG_WRITE(map->status, temp);
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REG_READ(map->status);
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gma_crtc_load_lut(crtc);
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/* Give the overlay scaler a chance to enable
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* if it's on this pipe */
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/* psb_intel_crtc_dpms_video(crtc, true); TODO */
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break;
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case DRM_MODE_DPMS_OFF:
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if (!psb_intel_crtc->active)
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break;
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psb_intel_crtc->active = false;
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/* Give the overlay scaler a chance to disable
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* if it's on this pipe */
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/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
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/* Disable the VGA plane that we never use */
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REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
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/* Turn off vblank interrupts */
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drm_vblank_off(dev, pipe);
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/* Wait for vblank for the disable to take effect */
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gma_wait_for_vblank(dev);
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/* Disable plane */
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temp = REG_READ(map->cntr);
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if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
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REG_WRITE(map->cntr,
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temp & ~DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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REG_WRITE(map->base, REG_READ(map->base));
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REG_READ(map->base);
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}
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/* Disable pipe */
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temp = REG_READ(map->conf);
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if ((temp & PIPEACONF_ENABLE) != 0) {
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REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
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REG_READ(map->conf);
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}
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/* Wait for vblank for the disable to take effect. */
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gma_wait_for_vblank(dev);
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udelay(150);
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/* Disable DPLL */
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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}
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/* Wait for the clocks to turn off. */
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udelay(150);
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break;
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}
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/* FIXME: Uncomment this when we move cdv to generic dpms
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if (IS_CDV(dev))
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cdv_intel_update_watermark(dev, crtc);
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*/
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/* Set FIFO watermarks */
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REG_WRITE(DSPARB, 0x3F3E);
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}
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bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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void gma_crtc_prepare(struct drm_crtc *crtc)
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{
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struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
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crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
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}
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void gma_crtc_commit(struct drm_crtc *crtc)
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{
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struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
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crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
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}
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void gma_crtc_disable(struct drm_crtc *crtc)
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{
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struct gtt_range *gt;
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struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
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crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
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if (crtc->fb) {
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gt = to_psb_fb(crtc->fb)->gtt;
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psb_gtt_unpin(gt);
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}
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}
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void gma_crtc_destroy(struct drm_crtc *crtc)
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{
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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kfree(psb_intel_crtc->crtc_state);
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drm_crtc_cleanup(crtc);
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kfree(psb_intel_crtc);
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}
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#define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
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bool gma_pll_is_valid(struct drm_crtc *crtc,
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@ -61,6 +61,20 @@ struct gma_clock_funcs {
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/* Common pipe related functions */
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extern bool gma_pipe_has_type(struct drm_crtc *crtc, int type);
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extern void gma_wait_for_vblank(struct drm_device *dev);
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extern int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb);
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extern void gma_crtc_load_lut(struct drm_crtc *crtc);
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extern void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, u32 start, u32 size);
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extern void gma_crtc_dpms(struct drm_crtc *crtc, int mode);
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extern bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode);
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extern void gma_crtc_prepare(struct drm_crtc *crtc);
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extern void gma_crtc_commit(struct drm_crtc *crtc);
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extern void gma_crtc_disable(struct drm_crtc *crtc);
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extern void gma_crtc_destroy(struct drm_crtc *crtc);
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/* Common clock related functions */
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extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
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