mirror of
https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
powerpc: rename dma_direct_ to dma_nommu_
We want to use the dma_direct_ namespace for a generic implementation, so rename powerpc to the second best choice: dma_nommu_. Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
parent
bf15f90b07
commit
2d9d6f6c9e
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@ -19,13 +19,13 @@
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#include <asm/swiotlb.h>
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/* Some dma direct funcs must be visible for use in other dma_ops */
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extern void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
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extern void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs);
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extern void __dma_direct_free_coherent(struct device *dev, size_t size,
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extern void __dma_nommu_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs);
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extern int dma_direct_mmap_coherent(struct device *dev,
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extern int dma_nommu_mmap_coherent(struct device *dev,
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struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t handle,
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size_t size, unsigned long attrs);
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@ -73,7 +73,7 @@ static inline unsigned long device_to_mask(struct device *dev)
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#ifdef CONFIG_PPC64
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extern struct dma_map_ops dma_iommu_ops;
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#endif
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extern const struct dma_map_ops dma_direct_ops;
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extern const struct dma_map_ops dma_nommu_ops;
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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{
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@ -114,7 +114,7 @@ int dma_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
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struct dma_map_ops dma_iommu_ops = {
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.alloc = dma_iommu_alloc_coherent,
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.free = dma_iommu_free_coherent,
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.mmap = dma_direct_mmap_coherent,
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.mmap = dma_nommu_mmap_coherent,
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.map_sg = dma_iommu_map_sg,
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.unmap_sg = dma_iommu_unmap_sg,
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.dma_supported = dma_iommu_dma_supported,
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@ -47,9 +47,9 @@ static u64 swiotlb_powerpc_get_required(struct device *dev)
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* for everything else.
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*/
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const struct dma_map_ops swiotlb_dma_ops = {
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.alloc = __dma_direct_alloc_coherent,
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.free = __dma_direct_free_coherent,
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.mmap = dma_direct_mmap_coherent,
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.alloc = __dma_nommu_alloc_coherent,
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.free = __dma_nommu_free_coherent,
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.mmap = dma_nommu_mmap_coherent,
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.map_sg = swiotlb_map_sg_attrs,
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.unmap_sg = swiotlb_unmap_sg_attrs,
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.dma_supported = swiotlb_dma_supported,
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@ -40,7 +40,7 @@ static u64 __maybe_unused get_pfn_limit(struct device *dev)
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return pfn;
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}
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static int dma_direct_dma_supported(struct device *dev, u64 mask)
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static int dma_nommu_dma_supported(struct device *dev, u64 mask)
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{
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#ifdef CONFIG_PPC64
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u64 limit = get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
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@ -62,7 +62,7 @@ static int dma_direct_dma_supported(struct device *dev, u64 mask)
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#endif
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}
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void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
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void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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@ -119,7 +119,7 @@ void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
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#endif
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}
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void __dma_direct_free_coherent(struct device *dev, size_t size,
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void __dma_nommu_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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@ -130,7 +130,7 @@ void __dma_direct_free_coherent(struct device *dev, size_t size,
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#endif
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}
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static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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static void *dma_nommu_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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@ -139,8 +139,8 @@ static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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/* The coherent mask may be smaller than the real mask, check if
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* we can really use the direct ops
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*/
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if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
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return __dma_direct_alloc_coherent(dev, size, dma_handle,
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if (dma_nommu_dma_supported(dev, dev->coherent_dma_mask))
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return __dma_nommu_alloc_coherent(dev, size, dma_handle,
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flag, attrs);
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/* Ok we can't ... do we have an iommu ? If not, fail */
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@ -154,15 +154,15 @@ static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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dev_to_node(dev));
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}
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static void dma_direct_free_coherent(struct device *dev, size_t size,
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static void dma_nommu_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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struct iommu_table *iommu;
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/* See comments in dma_direct_alloc_coherent() */
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if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
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return __dma_direct_free_coherent(dev, size, vaddr, dma_handle,
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/* See comments in dma_nommu_alloc_coherent() */
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if (dma_nommu_dma_supported(dev, dev->coherent_dma_mask))
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return __dma_nommu_free_coherent(dev, size, vaddr, dma_handle,
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attrs);
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/* Maybe we used an iommu ... */
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iommu = get_iommu_table_base(dev);
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@ -175,7 +175,7 @@ static void dma_direct_free_coherent(struct device *dev, size_t size,
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iommu_free_coherent(iommu, size, vaddr, dma_handle);
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}
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int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
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int dma_nommu_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t handle, size_t size,
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unsigned long attrs)
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{
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@ -193,7 +193,7 @@ int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
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vma->vm_page_prot);
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}
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static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
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static int dma_nommu_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction direction,
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unsigned long attrs)
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{
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@ -213,13 +213,13 @@ static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
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return nents;
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}
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static void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sg,
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static void dma_nommu_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction,
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unsigned long attrs)
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{
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}
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static u64 dma_direct_get_required_mask(struct device *dev)
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static u64 dma_nommu_get_required_mask(struct device *dev)
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{
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u64 end, mask;
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@ -231,7 +231,7 @@ static u64 dma_direct_get_required_mask(struct device *dev)
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return mask;
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}
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static inline dma_addr_t dma_direct_map_page(struct device *dev,
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static inline dma_addr_t dma_nommu_map_page(struct device *dev,
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struct page *page,
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unsigned long offset,
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size_t size,
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@ -246,7 +246,7 @@ static inline dma_addr_t dma_direct_map_page(struct device *dev,
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return page_to_phys(page) + offset + get_dma_offset(dev);
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}
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static inline void dma_direct_unmap_page(struct device *dev,
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static inline void dma_nommu_unmap_page(struct device *dev,
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dma_addr_t dma_address,
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size_t size,
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enum dma_data_direction direction,
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@ -255,7 +255,7 @@ static inline void dma_direct_unmap_page(struct device *dev,
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}
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#ifdef CONFIG_NOT_COHERENT_CACHE
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static inline void dma_direct_sync_sg(struct device *dev,
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static inline void dma_nommu_sync_sg(struct device *dev,
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struct scatterlist *sgl, int nents,
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enum dma_data_direction direction)
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{
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@ -266,7 +266,7 @@ static inline void dma_direct_sync_sg(struct device *dev,
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__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
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}
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static inline void dma_direct_sync_single(struct device *dev,
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static inline void dma_nommu_sync_single(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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@ -274,24 +274,24 @@ static inline void dma_direct_sync_single(struct device *dev,
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}
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#endif
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const struct dma_map_ops dma_direct_ops = {
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.alloc = dma_direct_alloc_coherent,
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.free = dma_direct_free_coherent,
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.mmap = dma_direct_mmap_coherent,
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.map_sg = dma_direct_map_sg,
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.unmap_sg = dma_direct_unmap_sg,
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.dma_supported = dma_direct_dma_supported,
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.map_page = dma_direct_map_page,
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.unmap_page = dma_direct_unmap_page,
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.get_required_mask = dma_direct_get_required_mask,
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const struct dma_map_ops dma_nommu_ops = {
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.alloc = dma_nommu_alloc_coherent,
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.free = dma_nommu_free_coherent,
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.mmap = dma_nommu_mmap_coherent,
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.map_sg = dma_nommu_map_sg,
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.unmap_sg = dma_nommu_unmap_sg,
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.dma_supported = dma_nommu_dma_supported,
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.map_page = dma_nommu_map_page,
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.unmap_page = dma_nommu_unmap_page,
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.get_required_mask = dma_nommu_get_required_mask,
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#ifdef CONFIG_NOT_COHERENT_CACHE
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.sync_single_for_cpu = dma_direct_sync_single,
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.sync_single_for_device = dma_direct_sync_single,
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.sync_sg_for_cpu = dma_direct_sync_sg,
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.sync_sg_for_device = dma_direct_sync_sg,
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.sync_single_for_cpu = dma_nommu_sync_single,
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.sync_single_for_device = dma_nommu_sync_single,
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.sync_sg_for_cpu = dma_nommu_sync_sg,
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.sync_sg_for_device = dma_nommu_sync_sg,
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#endif
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};
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EXPORT_SYMBOL(dma_direct_ops);
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EXPORT_SYMBOL(dma_nommu_ops);
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int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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* is no dma_op->set_coherent_mask() so we have to do
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* things the hard way:
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*/
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if (get_dma_ops(dev) != &dma_direct_ops ||
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if (get_dma_ops(dev) != &dma_nommu_ops ||
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get_iommu_table_base(dev) == NULL ||
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!dma_iommu_dma_supported(dev, mask))
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return -EIO;
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@ -60,7 +60,7 @@ resource_size_t isa_mem_base;
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EXPORT_SYMBOL(isa_mem_base);
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static const struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
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static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
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void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
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{
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@ -791,7 +791,7 @@ void arch_setup_pdev_archdata(struct platform_device *pdev)
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{
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pdev->archdata.dma_mask = DMA_BIT_MASK(32);
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pdev->dev.dma_mask = &pdev->archdata.dma_mask;
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set_dma_ops(&pdev->dev, &dma_direct_ops);
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set_dma_ops(&pdev->dev, &dma_nommu_ops);
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}
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static __init void print_system_info(void)
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@ -541,7 +541,7 @@ static struct cbe_iommu *cell_iommu_for_node(int nid)
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return NULL;
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}
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static unsigned long cell_dma_direct_offset;
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static unsigned long cell_dma_nommu_offset;
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static unsigned long dma_iommu_fixed_base;
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device_to_mask(dev), flag,
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dev_to_node(dev));
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else
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return dma_direct_ops.alloc(dev, size, dma_handle, flag,
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return dma_nommu_ops.alloc(dev, size, dma_handle, flag,
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attrs);
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}
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@ -592,7 +592,7 @@ static void dma_fixed_free_coherent(struct device *dev, size_t size,
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iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
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dma_handle);
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else
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dma_direct_ops.free(dev, size, vaddr, dma_handle, attrs);
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dma_nommu_ops.free(dev, size, vaddr, dma_handle, attrs);
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}
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static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page,
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unsigned long attrs)
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{
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if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
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return dma_direct_ops.map_page(dev, page, offset, size,
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return dma_nommu_ops.map_page(dev, page, offset, size,
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direction, attrs);
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else
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return iommu_map_page(dev, cell_get_iommu_table(dev), page,
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@ -614,7 +614,7 @@ static void dma_fixed_unmap_page(struct device *dev, dma_addr_t dma_addr,
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unsigned long attrs)
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{
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if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
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dma_direct_ops.unmap_page(dev, dma_addr, size, direction,
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dma_nommu_ops.unmap_page(dev, dma_addr, size, direction,
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attrs);
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else
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iommu_unmap_page(cell_get_iommu_table(dev), dma_addr, size,
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@ -626,7 +626,7 @@ static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg,
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unsigned long attrs)
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{
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if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
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return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
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return dma_nommu_ops.map_sg(dev, sg, nents, direction, attrs);
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else
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return ppc_iommu_map_sg(dev, cell_get_iommu_table(dev), sg,
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nents, device_to_mask(dev),
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unsigned long attrs)
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{
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if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
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dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
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dma_nommu_ops.unmap_sg(dev, sg, nents, direction, attrs);
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else
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ppc_iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents,
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direction, attrs);
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@ -661,8 +661,8 @@ static void cell_dma_dev_setup(struct device *dev)
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{
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if (get_pci_dma_ops() == &dma_iommu_ops)
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set_iommu_table_base(dev, cell_get_iommu_table(dev));
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else if (get_pci_dma_ops() == &dma_direct_ops)
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set_dma_offset(dev, cell_dma_direct_offset);
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else if (get_pci_dma_ops() == &dma_nommu_ops)
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set_dma_offset(dev, cell_dma_nommu_offset);
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else
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BUG();
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}
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@ -810,14 +810,14 @@ static int __init cell_iommu_init_disabled(void)
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unsigned long base = 0, size;
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/* When no iommu is present, we use direct DMA ops */
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set_pci_dma_ops(&dma_direct_ops);
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set_pci_dma_ops(&dma_nommu_ops);
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/* First make sure all IOC translation is turned off */
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cell_disable_iommus();
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/* If we have no Axon, we set up the spider DMA magic offset */
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if (of_find_node_by_name(NULL, "axon") == NULL)
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cell_dma_direct_offset = SPIDER_DMA_OFFSET;
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cell_dma_nommu_offset = SPIDER_DMA_OFFSET;
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/* Now we need to check to see where the memory is mapped
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* in PCI space. We assume that all busses use the same dma
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@ -851,13 +851,13 @@ static int __init cell_iommu_init_disabled(void)
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return -ENODEV;
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}
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cell_dma_direct_offset += base;
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cell_dma_nommu_offset += base;
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if (cell_dma_direct_offset != 0)
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if (cell_dma_nommu_offset != 0)
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cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
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printk("iommu: disabled, direct DMA offset is 0x%lx\n",
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cell_dma_direct_offset);
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cell_dma_nommu_offset);
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return 0;
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}
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@ -186,7 +186,7 @@ static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
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*/
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if (dev->vendor == 0x1959 && dev->device == 0xa007 &&
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!firmware_has_feature(FW_FEATURE_LPAR)) {
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dev->dev.dma_ops = &dma_direct_ops;
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dev->dev.dma_ops = &dma_nommu_ops;
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/*
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||||
* Set the coherent DMA mask to prevent the iommu
|
||||
* being used unnecessarily
|
||||
|
|
|
@ -363,7 +363,7 @@ static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
|
|||
return 0;
|
||||
|
||||
/* We use the direct ops for localbus */
|
||||
dev->dma_ops = &dma_direct_ops;
|
||||
dev->dma_ops = &dma_nommu_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1850,7 +1850,7 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
|
|||
|
||||
if (bypass) {
|
||||
dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
|
||||
set_dma_ops(&pdev->dev, &dma_direct_ops);
|
||||
set_dma_ops(&pdev->dev, &dma_nommu_ops);
|
||||
} else {
|
||||
/*
|
||||
* If the device can't set the TCE bypass bit but still wants
|
||||
|
@ -1868,7 +1868,7 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
|
|||
return rc;
|
||||
/* 4GB offset bypasses 32-bit space */
|
||||
set_dma_offset(&pdev->dev, (1ULL << 32));
|
||||
set_dma_ops(&pdev->dev, &dma_direct_ops);
|
||||
set_dma_ops(&pdev->dev, &dma_nommu_ops);
|
||||
} else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
|
||||
/*
|
||||
* Fail the request if a DMA mask between 32 and 64 bits
|
||||
|
|
|
@ -1231,7 +1231,7 @@ static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
|
|||
if (dma_offset != 0) {
|
||||
dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
|
||||
set_dma_offset(dev, dma_offset);
|
||||
set_dma_ops(dev, &dma_direct_ops);
|
||||
set_dma_ops(dev, &dma_nommu_ops);
|
||||
ddw_enabled = true;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -618,7 +618,7 @@ static u64 vio_dma_get_required_mask(struct device *dev)
|
|||
static const struct dma_map_ops vio_dma_mapping_ops = {
|
||||
.alloc = vio_dma_iommu_alloc_coherent,
|
||||
.free = vio_dma_iommu_free_coherent,
|
||||
.mmap = dma_direct_mmap_coherent,
|
||||
.mmap = dma_nommu_mmap_coherent,
|
||||
.map_sg = vio_dma_iommu_map_sg,
|
||||
.unmap_sg = vio_dma_iommu_unmap_sg,
|
||||
.map_page = vio_dma_iommu_map_page,
|
||||
|
|
|
@ -402,7 +402,7 @@ static int dart_dma_set_mask(struct device *dev, u64 dma_mask)
|
|||
*/
|
||||
if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) {
|
||||
dev_info(dev, "Using 64-bit DMA iommu bypass\n");
|
||||
set_dma_ops(dev, &dma_direct_ops);
|
||||
set_dma_ops(dev, &dma_nommu_ops);
|
||||
} else {
|
||||
dev_info(dev, "Using 32-bit DMA via iommu\n");
|
||||
set_dma_ops(dev, &dma_iommu_ops);
|
||||
|
@ -446,7 +446,7 @@ void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops)
|
|||
controller_ops->dma_bus_setup = NULL;
|
||||
|
||||
/* Setup pci_dma ops */
|
||||
set_pci_dma_ops(&dma_direct_ops);
|
||||
set_pci_dma_ops(&dma_nommu_ops);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
|
@ -135,7 +135,7 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
|
|||
* mapping that allows addressing any RAM address from across PCI.
|
||||
*/
|
||||
if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
|
||||
set_dma_ops(dev, &dma_direct_ops);
|
||||
set_dma_ops(dev, &dma_nommu_ops);
|
||||
set_dma_offset(dev, pci64_dma_offset);
|
||||
}
|
||||
|
||||
|
|
|
@ -54,7 +54,7 @@ static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
|
|||
return false;
|
||||
}
|
||||
|
||||
set_dma_ops(&dev->dev, &dma_direct_ops);
|
||||
set_dma_ops(&dev->dev, &dma_nommu_ops);
|
||||
set_dma_offset(&dev->dev, PAGE_OFFSET);
|
||||
|
||||
return _cxl_pci_associate_default_context(dev, afu);
|
||||
|
|
Loading…
Reference in a new issue