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mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver
Previously added spi-mem interface is now used instead of older approach. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
d5433def31
commit
2d30ac5ed6
1 changed files with 18 additions and 73 deletions
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@ -766,27 +766,9 @@ static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
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static int atmel_qspi_init(struct atmel_qspi *aq)
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{
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unsigned long src_rate;
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u32 mr, scr, scbr;
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/* Reset the QSPI controller */
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qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
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/* Set the QSPI controller in Serial Memory Mode */
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mr = QSPI_MR_NBBITS(8) | QSPI_MR_SMM;
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qspi_writel(aq, QSPI_MR, mr);
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src_rate = clk_get_rate(aq->clk);
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if (!src_rate)
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return -EINVAL;
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/* Compute the QSPI baudrate */
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scbr = DIV_ROUND_UP(src_rate, aq->clk_rate);
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if (scbr > 0)
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scbr--;
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scr = QSPI_SCR_SCBR(scbr);
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qspi_writel(aq, QSPI_SCR, scr);
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/* Enable the QSPI controller */
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qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
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@ -814,38 +796,25 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
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static int atmel_qspi_probe(struct platform_device *pdev)
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{
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const struct spi_nor_hwcaps hwcaps = {
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.mask = SNOR_HWCAPS_READ |
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SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_READ_1_1_2 |
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SNOR_HWCAPS_READ_1_2_2 |
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SNOR_HWCAPS_READ_2_2_2 |
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SNOR_HWCAPS_READ_1_1_4 |
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SNOR_HWCAPS_READ_1_4_4 |
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SNOR_HWCAPS_READ_4_4_4 |
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SNOR_HWCAPS_PP |
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SNOR_HWCAPS_PP_1_1_4 |
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SNOR_HWCAPS_PP_1_4_4 |
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SNOR_HWCAPS_PP_4_4_4,
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};
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struct device_node *child, *np = pdev->dev.of_node;
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struct spi_controller *ctrl;
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struct atmel_qspi *aq;
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struct resource *res;
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struct spi_nor *nor;
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struct mtd_info *mtd;
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int irq, err = 0;
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if (of_get_child_count(np) != 1)
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return -ENODEV;
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child = of_get_next_child(np, NULL);
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ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
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if (!ctrl)
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return -ENOMEM;
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aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL);
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if (!aq) {
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err = -ENOMEM;
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goto exit;
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}
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ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
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ctrl->setup = atmel_qspi_setup;
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ctrl->bus_num = -1;
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ctrl->mem_ops = &atmel_qspi_mem_ops;
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ctrl->num_chipselect = 1;
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ctrl->dev.of_node = pdev->dev.of_node;
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platform_set_drvdata(pdev, ctrl);
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aq = spi_controller_get_devdata(ctrl);
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platform_set_drvdata(pdev, aq);
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init_completion(&aq->cmd_completion);
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aq->pdev = pdev;
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@ -894,54 +863,30 @@ static int atmel_qspi_probe(struct platform_device *pdev)
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if (err)
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goto disable_clk;
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/* Setup the spi-nor */
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nor = &aq->nor;
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mtd = &nor->mtd;
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nor->dev = &pdev->dev;
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spi_nor_set_flash_node(nor, child);
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nor->priv = aq;
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mtd->priv = nor;
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nor->read_reg = atmel_qspi_read_reg;
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nor->write_reg = atmel_qspi_write_reg;
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nor->read = atmel_qspi_read;
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nor->write = atmel_qspi_write;
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nor->erase = atmel_qspi_erase;
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err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate);
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if (err < 0)
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goto disable_clk;
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err = atmel_qspi_init(aq);
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if (err)
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goto disable_clk;
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err = spi_nor_scan(nor, NULL, &hwcaps);
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err = spi_register_controller(ctrl);
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if (err)
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goto disable_clk;
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err = mtd_device_register(mtd, NULL, 0);
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if (err)
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goto disable_clk;
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of_node_put(child);
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return 0;
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disable_clk:
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clk_disable_unprepare(aq->clk);
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exit:
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of_node_put(child);
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spi_controller_put(ctrl);
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return err;
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}
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static int atmel_qspi_remove(struct platform_device *pdev)
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{
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struct atmel_qspi *aq = platform_get_drvdata(pdev);
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struct spi_controller *ctrl = platform_get_drvdata(pdev);
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struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
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mtd_device_unregister(&aq->nor.mtd);
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spi_unregister_controller(ctrl);
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qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
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clk_disable_unprepare(aq->clk);
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return 0;
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