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https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
powerpc: clean inclusions of asm/feature-fixups.h
files not using feature fixup don't need asm/feature-fixups.h files using feature fixup need asm/feature-fixups.h Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
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5c35a02c54
commit
2c86cd188f
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@ -4,7 +4,6 @@
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#include <linux/types.h>
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#include <asm/feature-fixups.h>
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#include <uapi/asm/cputable.h>
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#include <asm/asm-const.h>
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@ -16,6 +16,7 @@
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#include <linux/threads.h>
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#include <asm/ppc-opcode.h>
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#include <asm/feature-fixups.h>
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#define PPC_DBELL_MSG_BRDCAST (0x04000000)
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#define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36))
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@ -10,7 +10,6 @@
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*/
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#include <linux/types.h>
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#include <asm/feature-fixups.h>
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#include <uapi/asm/cputable.h>
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#ifdef CONFIG_PPC_DT_CPU_FTRS
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@ -35,6 +35,7 @@
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* implementations as possible.
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*/
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#include <asm/head-64.h>
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#include <asm/feature-fixups.h>
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/* PACA save area offsets (exgen, exmc, etc) */
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#define EX_R9 0
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@ -14,7 +14,6 @@
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#ifdef __KERNEL__
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#include <asm/feature-fixups.h>
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#include <asm/asm-const.h>
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/* firmware feature bitmask values */
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@ -9,6 +9,8 @@
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#ifndef ASM_KVM_BOOKE_HV_ASM_H
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#define ASM_KVM_BOOKE_HV_ASM_H
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#include <asm/feature-fixups.h>
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#ifdef __ASSEMBLY__
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/*
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@ -5,7 +5,6 @@
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#include <linux/types.h>
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#include <asm/feature-fixups.h>
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#include <asm/asm-const.h>
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/*
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@ -9,6 +9,7 @@
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#include <asm/processor.h>
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#include <asm/ppc-opcode.h>
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#include <asm/firmware.h>
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#include <asm/feature-fixups.h>
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#ifdef __ASSEMBLY__
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@ -14,6 +14,7 @@
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#include <linux/stringify.h>
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#include <asm/cputable.h>
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#include <asm/asm-const.h>
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#include <asm/feature-fixups.h>
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/* Pickup Book E specific registers. */
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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
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@ -16,6 +16,7 @@
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/feature-fixups.h>
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_GLOBAL(__setup_cpu_603)
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mflr r5
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/asm-405.h>
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#include <asm/feature-fixups.h>
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/*
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* MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
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#else
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#include <asm/exception-64e.h>
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#endif
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#include <asm/feature-fixups.h>
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/*
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* System calls.
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#include <asm/hw_irq.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_booke_hv_asm.h>
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#include <asm/feature-fixups.h>
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/* XXX This will ultimately add space for a special exception save
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* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
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@ -18,6 +18,7 @@
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#include <asm/ptrace.h>
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#include <asm/cpuidle.h>
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#include <asm/head-64.h>
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#include <asm/feature-fixups.h>
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/*
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* There are a few constraints to be concerned with.
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#ifdef CONFIG_VSX
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#define __REST_32FPVSRS(n,c,base) \
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#include <asm/bug.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
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#define LOAD_BAT(n, reg, RA, RB) \
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#include <asm/cputhreads.h>
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#include <asm/ppc-opcode.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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/* The physical memory is laid out such that the secondary processor
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* spin code sits at 0x0000...0x00ff. On server, the vectors follow
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#include <asm/cache.h>
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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#include "head_booke.h"
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/* As with the other PowerPC ports, it is expected that when code
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/feature-fixups.h>
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.text
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#include <asm/book3s/64/mmu-hash.h>
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#include <asm/mmu.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#undef DEBUG
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/feature-fixups.h>
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.text
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#include <asm/asm-offsets.h>
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#include <asm/irqflags.h>
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#include <asm/hw_irq.h>
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#include <asm/feature-fixups.h>
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#undef DEBUG
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#include <asm/ppc_asm.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/feature-fixups.h>
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/* Usage:
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#include <asm/bug.h>
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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.text
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#include <asm/ptrace.h>
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#include <asm/mmu.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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.text
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#include <asm/cpu_has_feature.h>
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#include <asm/asm-prototypes.h>
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#include <asm/kdump.h>
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#include <asm/feature-fixups.h>
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#define DBG(fmt...)
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#include <asm/opal.h>
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#include <asm/cputhreads.h>
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#include <asm/hw_irq.h>
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#include <asm/feature-fixups.h>
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#include "setup.h"
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mmu.h>
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#include <asm/feature-fixups.h>
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/*
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* Structure for storing CPU registers on the save area.
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/feature-fixups.h>
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/*
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* Structure for storing CPU registers on the save area.
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#include <asm/reg.h>
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#include <asm/bug.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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#ifdef CONFIG_VSX
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/* See fpu.S, this is borrowed from there */
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*/
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#define SHADOW_SLB_ENTRY_LEN 0x10
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#define OFFSET_ESID(x) (SHADOW_SLB_ENTRY_LEN * x)
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#include <asm/exception-64s.h>
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#include <asm/ppc-opcode.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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/*****************************************************************************
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* *
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#include <asm/xive-regs.h>
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#include <asm/thread_info.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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/* Sign-extend HDEC if not on POWER9 */
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#define EXTEND_HDEC(reg) \
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/* Real mode helpers */
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#if defined(CONFIG_PPC_BOOK3S_64)
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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.section ".toc","aw"
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PPC64_CACHES:
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#ifdef __BIG_ENDIAN__
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#define sLd sld /* Shift towards low-numbered address. */
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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/* Note: This code relies on -mminimal-toc */
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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.align 7
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_GLOBAL_TOC(memcpy)
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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#ifdef CONFIG_SMP
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.section .bss
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#include <asm/udbg.h>
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#include <asm/kexec.h>
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#include <asm/ppc-opcode.h>
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#include <asm/feature-fixups.h>
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#include <misc/cxl-base.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/firmware.h>
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#include <asm/feature-fixups.h>
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/*
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* This macro generates asm code to compute the VSID scramble
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#include <asm/ppc-opcode.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_booke_hv_asm.h>
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#include <asm/feature-fixups.h>
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#ifdef CONFIG_PPC_64K_PAGES
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#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
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#include <asm/processor.h>
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#include <asm/bug.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#if defined(CONFIG_40x)
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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#include <asm/feature-fixups.h>
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/*
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* Flush and disable all data caches (dL1, L2, L3). This is used
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/mmu.h>
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#include <asm/feature-fixups.h>
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#define MAGIC 0x4c617273 /* 'Lars' */
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#include <asm/asm-offsets.h>
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#include <asm/opal.h>
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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.section ".text"
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#include <asm/feature-fixups.h>
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.section ".text"
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1
tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h
Symbolic link
1
tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h
Symbolic link
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../../../../../../arch/powerpc/include/asm/feature-fixups.h
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