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powerpc/fsl_msi: add support for "msi-address-64" property
Add support for the msi-address-64 property of a PCI node. This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).
In commit 3da34aae
("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly. These fields are replace with a single field, msiir_offset,
to reflect the new meaning.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
4511680613
commit
2bcd1c0cfc
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@ -25,6 +25,16 @@ Required properties:
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are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
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to MPIC.
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Optional properties:
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- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
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is used for MSI messaging. The address of MSIIR in PCI address space is
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the MSI message address.
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This property may be used in virtualized environments where the hypervisor
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has created an alternate mapping for the MSIR block. See below for an
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explanation.
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Example:
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msi@41600 {
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compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
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@ -41,3 +51,35 @@ Example:
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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The Freescale hypervisor and msi-address-64
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-------------------------------------------
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Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
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Freescale MSI driver calculates the address of MSIIR (in the MSI register
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block) and sets that address as the MSI message address.
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In a virtualized environment, the hypervisor may need to create an IOMMU
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mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
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because of hardware limitations of the Peripheral Access Management Unit
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(PAMU), which is currently the only IOMMU that the hypervisor supports.
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The ATMU is programmed with the guest physical address, and the PAMU
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intercepts transactions and reroutes them to the true physical address.
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In the PAMU, each PCI controller is given only one primary window. The
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PAMU restricts DMA operations so that they can only occur within a window.
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Because PCI devices must be able to DMA to memory, the primary window must
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be used to cover all of the guest's memory space.
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PAMU primary windows can be divided into 256 subwindows, and each
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subwindow can have its own address mapping ("guest physical" to "true
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physical"). However, each subwindow has to have the same alignment, which
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means they cannot be located at just any address. Because of these
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restrictions, it is usually impossible to create a 4KB subwindow that
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covers MSIIR where it's normally located.
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Therefore, the hypervisor has to create a subwindow inside the same
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primary window used for memory, but mapped to the MSIR block (where MSIIR
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lives). The first subwindow after the end of guest memory is used for
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this. The address specified in the msi-address-64 property is the PCI
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address of MSIIR. The hypervisor configures the PAMU to map that address to
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the true physical address of MSIIR.
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@ -30,7 +30,7 @@ LIST_HEAD(msi_head);
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struct fsl_msi_feature {
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u32 fsl_pic_ip;
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u32 msiir_offset;
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u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
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};
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struct fsl_msi_cascade_data {
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@ -126,10 +126,19 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
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{
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struct fsl_msi *msi_data = fsl_msi_data;
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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u64 base = fsl_pci_immrbar_base(hose);
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u64 address; /* Physical address of the MSIIR */
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int len;
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const u64 *reg;
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msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base);
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msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base);
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/* If the msi-address-64 property exists, then use it */
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reg = of_get_property(hose->dn, "msi-address-64", &len);
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if (reg && (len == sizeof(u64)))
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address = be64_to_cpup(reg);
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else
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address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
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msg->address_lo = lower_32_bits(address);
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msg->address_hi = upper_32_bits(address);
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msg->data = hwirq;
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@ -359,8 +368,7 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
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msi->irqhost->host_data = msi;
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msi->msi_addr_hi = 0x0;
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msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
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msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff);
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rc = fsl_msi_init_allocator(msi);
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if (rc) {
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@ -28,8 +28,7 @@ struct fsl_msi {
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unsigned long cascade_irq;
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u32 msi_addr_lo;
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u32 msi_addr_hi;
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u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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void __iomem *msi_regs;
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u32 feature;
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int msi_virqs[NR_MSI_REG];
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