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audio: tlv320aic26: fix PLL register configuration

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The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz.  Use the clock value provided by the DAI_OPS
API for the calculation.

Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.

Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@ti.com>
This commit is contained in:
Michael Williamson 2011-05-20 10:26:06 -04:00 committed by Liam Girdwood
parent 4a787a3ff3
commit 2aba76f014
1 changed files with 11 additions and 3 deletions
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14
sound/soc/codecs/tlv320aic26.c
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@ -161,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
}
/* Configure PLL */
/**
* Configure PLL
* fsref = (mclk * PLLM) / 2048
* where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal)
*/
pval = 1;
jval = (fsref == 44100) ? 7 : 8;
dval = (fsref == 44100) ? 5264 : 1920;
/* compute J portion of multiplier */
jval = fsref / (aic26->mclk / 2048);
/* compute fractional DDDD component of multiplier */
dval = fsref - (jval * (aic26->mclk / 2048));
dval = (10000 * dval) / (aic26->mclk / 2048);
dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);
qval = 0;
reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);