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- mt8173 add cpufreq related nodes
supply nodes frequency/voltage operation table - mt2712 add cpufreq related nodes fixed regulator supply nodes frequency/voltage operation table - mt2712 add clock contoller nodes - mt2712 add scpsys node -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlo7nR8XHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00Nv2A/+Lw6UXhnIrINEv+LP9d5ECLIO QECRmHMYhyJDNAS3EjZR3phneYFKSKxdoAwF9prT0vaTZSvaGVShSg7RiN/sSNyR u7mOWrjDroXMLVw1stxLe25yLpO9nuw3ORf5kS1FE8CHeeC+6cJ6NPob/qEz9iUq BqcZJIrHzwWQASc3JpNwTcYnHRqweylyyKjrHF4mIzXoW7RpW/1yONjXc7hXapuB EggZRpHdM/1wv9HxBlsuPfH/NxHmA48DIS/kz+00tSKwpVJgKdSbTW7lFN99up8s 6HUx1qpd1Elh8q048c0Oe202ubYOwpDDO8REeFsqBFuseAXPogPzXPSusTghm8Ph orgmV3sOHvr2XWD7QeEUtVSfPV+JnGWFeJ/Bx9jAxIVQ3BmWkoHbuiq/kAZ/uK3s HvnaiaidiBnIygNE6OZIvKNbeoF40601+60VquKfydqoQ47mYR0+xN89Q5F4m6Q9 ugTLbHrDU00soPueODWi+AlLfarThIjU+7aqcPbya6sNJfA/HAtVmX/wpWc5kR9a rEuEzFUgAWQocfZNZXgAfQES67L32MFsTbK5B0gpTT2VgAFdmKNUnjq4AFX+kghk GHTHxz4s6iMoH6kdaU3BVkJIiUBSKXoCsnIRwD7QOxlSNNMdtwyugUxeXBzSQA4j 7EgwCT9WfCIXEfSP3Eo= =yHbI -----END PGP SIGNATURE----- Merge tag 'v4.15-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt Pull "arm64: Updates of aarch64 DTS for v4.15-next" from Matthias Brugger - mt8173 add cpufreq related nodes supply nodes frequency/voltage operation table - mt2712 add cpufreq related nodes fixed regulator supply nodes frequency/voltage operation table - mt2712 add clock contoller nodes - mt2712 add scpsys node * tag 'v4.15-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: Add power controller device node of MT2712 arm64: dts: mediatek: add mt2712 cpufreq related device nodes arm64: dts: mt2712: Add clock controller device nodes arm64: dts: mediatek: add mt8173 cpufreq related device nodes dt-bindings: soc: add MT2712 power dt-bindings
This commit is contained in:
Arnd Bergmann
commit
2939f96539
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@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
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- include/dt-bindings/power/mt8173-power.h
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- include/dt-bindings/power/mt6797-power.h
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- include/dt-bindings/power/mt2701-power.h
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- include/dt-bindings/power/mt2712-power.h
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- include/dt-bindings/power/mt7622-power.h
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Required properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-scpsys"
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- "mediatek,mt2712-scpsys"
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- "mediatek,mt6797-scpsys"
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- "mediatek,mt7622-scpsys"
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- "mediatek,mt8173-scpsys"
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@ -27,6 +29,7 @@ Required properties:
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These are clocks which hardware needs to be
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enabled before enabling certain power domains.
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Required clocks for MT2701: "mm", "mfg", "ethif"
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Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
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Required clocks for MT6797: "mm", "mfg", "vdec"
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Required clocks for MT7622: "hif_sel"
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Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
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@ -24,6 +24,33 @@ memory@40000000 {
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chosen {
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stdout-path = "serial0:921600n8";
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};
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cpus_fixed_vproc0: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vproc_buck0";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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};
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cpus_fixed_vproc1: fixedregulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "vproc_buck1";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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};
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};
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&cpu0 {
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proc-supply = <&cpus_fixed_vproc0>;
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};
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&cpu1 {
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proc-supply = <&cpus_fixed_vproc0>;
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};
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&cpu2 {
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proc-supply = <&cpus_fixed_vproc1>;
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};
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&uart0 {
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@ -5,8 +5,10 @@
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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#include <dt-bindings/clock/mt2712-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt2712-power.h>
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/ {
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compatible = "mediatek,mt2712";
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@ -14,6 +16,48 @@ / {
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#address-cells = <2>;
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#size-cells = <2>;
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <598000000>;
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opp-microvolt = <1000000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <1000000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <793000000>;
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opp-microvolt = <1000000>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <598000000>;
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opp-microvolt = <1000000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <1000000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <793000000>;
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opp-microvolt = <1000000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <897000000>;
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opp-microvolt = <1000000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <1000000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -39,6 +83,11 @@ cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x000>;
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clocks = <&mcucfg CLK_MCU_MP0_SEL>,
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<&topckgen CLK_TOP_F_MP0_PLL1>;
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clock-names = "cpu", "intermediate";
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proc-supply = <&cpus_fixed_vproc0>;
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operating-points-v2 = <&cluster0_opp>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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@ -47,6 +96,11 @@ cpu1: cpu@1 {
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compatible = "arm,cortex-a35";
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reg = <0x001>;
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enable-method = "psci";
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clocks = <&mcucfg CLK_MCU_MP0_SEL>,
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<&topckgen CLK_TOP_F_MP0_PLL1>;
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clock-names = "cpu", "intermediate";
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proc-supply = <&cpus_fixed_vproc0>;
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operating-points-v2 = <&cluster0_opp>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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@ -55,6 +109,11 @@ cpu2: cpu@200 {
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compatible = "arm,cortex-a72";
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reg = <0x200>;
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enable-method = "psci";
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clocks = <&mcucfg CLK_MCU_MP2_SEL>,
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<&topckgen CLK_TOP_F_BIG_PLL1>;
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clock-names = "cpu", "intermediate";
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proc-supply = <&cpus_fixed_vproc1>;
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operating-points-v2 = <&cluster1_opp>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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@ -98,6 +157,48 @@ sys_clk: dummyclk {
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#clock-cells = <0>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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clk32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "clk32k";
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};
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clkfpc: oscillator@2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "clkfpc";
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};
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clkaud_ext_i_0: oscillator@3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <6500000>;
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clock-output-names = "clkaud_ext_i_0";
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};
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clkaud_ext_i_1: oscillator@4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <196608000>;
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clock-output-names = "clkaud_ext_i_1";
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};
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clkaud_ext_i_2: oscillator@5 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <180633600>;
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clock-output-names = "clkaud_ext_i_2";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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@ -111,6 +212,39 @@ timer {
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(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt2712-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt2712-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt2712-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt2712-scpsys", "syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_JPGDEC_SEL>,
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<&topckgen CLK_TOP_A1SYS_HP_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>;
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clock-names = "mm", "mfg", "venc",
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"jpgdec", "audio", "vdec";
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infracfg = <&infracfg>;
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};
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uart5: serial@1000f000 {
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compatible = "mediatek,mt2712-uart",
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"mediatek,mt6577-uart";
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@ -121,6 +255,18 @@ uart5: serial@1000f000 {
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status = "disabled";
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2712-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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mcucfg: syscon@10220000 {
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compatible = "mediatek,mt2712-mcucfg", "syscon";
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reg = <0 0x10220000 0 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@10220a80 {
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compatible = "mediatek,mt2712-sysirq",
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"mediatek,mt6577-sysirq";
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@ -192,5 +338,47 @@ uart4: serial@11019000 {
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mfgcfg: syscon@13000000 {
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compatible = "mediatek,mt2712-mfgcfg", "syscon";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt2712-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt2712-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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bdpsys: syscon@15010000 {
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compatible = "mediatek,mt2712-bdpsys", "syscon";
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reg = <0 0x15010000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt2712-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: syscon@18000000 {
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compatible = "mediatek,mt2712-vencsys", "syscon";
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reg = <0 0x18000000 0 0x1000>;
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#clock-cells = <1>;
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};
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jpgdecsys: syscon@19000000 {
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compatible = "mediatek,mt2712-jpgdecsys", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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@ -74,6 +74,24 @@ &cec {
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status = "okay";
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};
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&cpu0 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
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&cpu1 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
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&cpu2 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
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};
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&cpu3 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
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};
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&dpi0 {
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status = "okay";
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};
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|
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@ -51,6 +51,80 @@ aliases {
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mdp_wrot1 = &mdp_wrot1;
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <859000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <908000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <983000>;
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};
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opp-1105000000 {
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opp-hz = /bits/ 64 <1105000000>;
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opp-microvolt = <1009000>;
|
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};
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opp-1209000000 {
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opp-hz = /bits/ 64 <1209000000>;
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opp-microvolt = <1034000>;
|
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};
|
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1057000>;
|
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};
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opp-1508000000 {
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opp-hz = /bits/ 64 <1508000000>;
|
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opp-microvolt = <1109000>;
|
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};
|
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opp-1703000000 {
|
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opp-hz = /bits/ 64 <1703000000>;
|
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opp-microvolt = <1125000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp-507000000 {
|
||||
opp-hz = /bits/ 64 <507000000>;
|
||||
opp-microvolt = <828000>;
|
||||
};
|
||||
opp-702000000 {
|
||||
opp-hz = /bits/ 64 <702000000>;
|
||||
opp-microvolt = <867000>;
|
||||
};
|
||||
opp-1001000000 {
|
||||
opp-hz = /bits/ 64 <1001000000>;
|
||||
opp-microvolt = <927000>;
|
||||
};
|
||||
opp-1209000000 {
|
||||
opp-hz = /bits/ 64 <1209000000>;
|
||||
opp-microvolt = <968000>;
|
||||
};
|
||||
opp-1404000000 {
|
||||
opp-hz = /bits/ 64 <1404000000>;
|
||||
opp-microvolt = <1007000>;
|
||||
};
|
||||
opp-1612000000 {
|
||||
opp-hz = /bits/ 64 <1612000000>;
|
||||
opp-microvolt = <1049000>;
|
||||
};
|
||||
opp-1807000000 {
|
||||
opp-hz = /bits/ 64 <1807000000>;
|
||||
opp-microvolt = <1089000>;
|
||||
};
|
||||
opp-2106000000 {
|
||||
opp-hz = /bits/ 64 <2106000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -81,6 +155,10 @@ cpu0: cpu@0 {
|
|||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
|
@ -89,6 +167,10 @@ cpu1: cpu@1 {
|
|||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
|
|
@ -97,6 +179,10 @@ cpu2: cpu@100 {
|
|||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
|
|
@ -105,6 +191,10 @@ cpu3: cpu@101 {
|
|||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
|
|
|
|||
26
include/dt-bindings/power/mt2712-power.h
Normal file
26
include/dt-bindings/power/mt2712-power.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (C) 2017 MediaTek Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H
|
||||
#define _DT_BINDINGS_POWER_MT2712_POWER_H
|
||||
|
||||
#define MT2712_POWER_DOMAIN_MM 0
|
||||
#define MT2712_POWER_DOMAIN_VDEC 1
|
||||
#define MT2712_POWER_DOMAIN_VENC 2
|
||||
#define MT2712_POWER_DOMAIN_ISP 3
|
||||
#define MT2712_POWER_DOMAIN_AUDIO 4
|
||||
#define MT2712_POWER_DOMAIN_USB 5
|
||||
#define MT2712_POWER_DOMAIN_USB2 6
|
||||
#define MT2712_POWER_DOMAIN_MFG 7
|
||||
|
||||
#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */
|
||||
Loading…
Reference in a new issue