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arm64: Workaround for Cortex-A55 erratum 1530923
Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a result of a speculative AT instruction. This may happen in the middle of a guest world switch while the relevant VMSA configuration is in an inconsistent state, leading to erroneous content being allocated into TLBs. The same workaround as is used for Cortex-A76 erratum 1165522 (WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this mandates the use of VHE on affected parts. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
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@ -88,6 +88,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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| ARM | Neoverse-N1 | #1349291 | N/A |
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@ -530,6 +530,19 @@ config ARM64_ERRATUM_1165522
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If unsure, say Y.
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If unsure, say Y.
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config ARM64_ERRATUM_1530923
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bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
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default y
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select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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help
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This option adds a workaround for ARM Cortex-A55 erratum 1530923.
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Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
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corrupted TLBs by speculating an AT instruction during a guest
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context switch.
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If unsure, say Y.
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config ARM64_ERRATUM_1286807
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config ARM64_ERRATUM_1286807
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bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
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bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
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default y
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default y
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@ -91,8 +91,8 @@ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm)
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write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);
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write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);
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/*
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/*
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* ARM erratum 1165522 requires the actual execution of the above
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* ARM errata 1165522 and 1530923 require the actual execution of the
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* before we can switch to the EL1/EL0 translation regime used by
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* above before we can switch to the EL1/EL0 translation regime used by
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* the guest.
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* the guest.
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*/
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
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@ -762,6 +762,10 @@ static const struct midr_range erratum_speculative_at_vhe_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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/* Cortex A76 r0p0 to r2p0 */
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/* Cortex A76 r0p0 to r2p0 */
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1530923
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/* Cortex A55 r0p0 to r2p0 */
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MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
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#endif
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#endif
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{},
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{},
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};
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};
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@ -895,7 +899,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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#endif
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE
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{
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{
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.desc = "ARM erratum 1165522",
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.desc = "ARM errata 1165522, 1530923",
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.capability = ARM64_WORKAROUND_SPECULATIVE_AT_VHE,
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.capability = ARM64_WORKAROUND_SPECULATIVE_AT_VHE,
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ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_vhe_list),
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ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_vhe_list),
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},
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},
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@ -158,8 +158,8 @@ static void deactivate_traps_vhe(void)
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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/*
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/*
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* ARM erratum 1165522 requires the actual execution of the above
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* ARM errata 1165522 and 1530923 require the actual execution of the
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* before we can switch to the EL2/EL0 translation regime used by
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* above before we can switch to the EL2/EL0 translation regime used by
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* the host.
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* the host.
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*/
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
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@ -25,8 +25,8 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) {
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if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) {
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/*
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/*
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* For CPUs that are affected by ARM erratum 1165522, we
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* For CPUs that are affected by ARM errata 1165522 or 1530923,
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* cannot trust stage-1 to be in a correct state at that
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* we cannot trust stage-1 to be in a correct state at that
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* point. Since we do not want to force a full load of the
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* point. Since we do not want to force a full load of the
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* vcpu state, we prevent the EL1 page-table walker to
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* vcpu state, we prevent the EL1 page-table walker to
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* allocate new TLBs. This is done by setting the EPD bits
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* allocate new TLBs. This is done by setting the EPD bits
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