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PCI: tegra: Fix host link initialization
Commitb9ac0f9dc8
("PCI: dwc: Move dw_pcie_setup_rc() to DWC common code") broke enumeration of downstream devices on Tegra: In non-working case (next-20201211): 0001:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad2 (rev a1) 0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13) 0005:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad0 (rev a1) In working case (v5.10-rc7): 0001:00:00.0 PCI bridge: Molex Incorporated Device 1ad2 (rev a1) 0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13) 0005:00:00.0 PCI bridge: Molex Incorporated Device 1ad0 (rev a1) 0005:01:00.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab) 0005:02:02.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab) 0005:03:00.0 USB controller: PLX Technology, Inc. Device 3380 (rev ab) The problem seems to be dw_pcie_setup_rc() is now called twice before and after the link up handling. The fix is to move Tegra's link up handling to .start_link() function like other DWC drivers. Tegra is a bit more complicated than others as it re-inits the whole DWC controller to retry the link. With this, the initialization ordering is restored to match the prior sequence. Fixes:b9ac0f9dc8
("PCI: dwc: Move dw_pcie_setup_rc() to DWC common code") Link: https://lore.kernel.org/r/20201218143905.1614098-1-robh@kernel.org Reported-by: Mian Yousaf Kaukab <ykaukab@suse.de> Tested-by: Mian Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Vidya Sagar <vidyas@nvidia.com>
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@ -853,12 +853,14 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
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dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
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}
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static void tegra_pcie_prepare_host(struct pcie_port *pp)
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static int tegra_pcie_dw_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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u32 val;
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pp->bridge->ops = &tegra_pci_ops;
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if (!pcie->pcie_cap_base)
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pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
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PCI_CAP_ID_EXP);
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@ -907,10 +909,24 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
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dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
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}
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dw_pcie_setup_rc(pp);
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clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
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return 0;
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}
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static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
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{
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u32 val, offset, speed, tmp;
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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struct pcie_port *pp = &pci->pp;
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bool retry = true;
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if (pcie->mode == DW_PCIE_EP_TYPE) {
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enable_irq(pcie->pex_rst_irq);
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return 0;
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}
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retry_link:
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/* Assert RST */
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val = appl_readl(pcie, APPL_PINMUX);
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val &= ~APPL_PINMUX_PEX_RST;
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@ -929,19 +945,10 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
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appl_writel(pcie, val, APPL_PINMUX);
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msleep(100);
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}
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static int tegra_pcie_dw_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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u32 val, tmp, offset, speed;
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pp->bridge->ops = &tegra_pci_ops;
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tegra_pcie_prepare_host(pp);
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if (dw_pcie_wait_for_link(pci)) {
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if (!retry)
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return 0;
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/*
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* There are some endpoints which can't get the link up if
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* root port has Data Link Feature (DLF) enabled.
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@ -975,10 +982,11 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
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val &= ~PCI_DLF_EXCHANGE_ENABLE;
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dw_pcie_writel_dbi(pci, offset, val);
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tegra_pcie_prepare_host(pp);
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tegra_pcie_dw_host_init(pp);
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dw_pcie_setup_rc(pp);
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if (dw_pcie_wait_for_link(pci))
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return 0;
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retry = false;
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goto retry_link;
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}
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speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
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@ -998,15 +1006,6 @@ static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
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return !!(val & PCI_EXP_LNKSTA_DLLLA);
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}
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static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
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{
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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enable_irq(pcie->pex_rst_irq);
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return 0;
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}
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static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)
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{
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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@ -2215,6 +2214,10 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
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goto fail_host_init;
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}
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ret = tegra_pcie_dw_start_link(&pcie->pci);
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if (ret < 0)
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goto fail_host_init;
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/* Restore MSI interrupt vector */
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dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
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pcie->msi_ctrl_int);
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