mirror of
https://github.com/torvalds/linux
synced 2024-09-30 00:10:51 +00:00
brcmsmac: remove nicpci.c
There is no code doing anything useful in nicpci.c anymore, so remove it. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Hauke Mehrtens
John W. Linville
parent
c496fe3a7f
commit
270e38d008
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@ -40,7 +40,6 @@ BRCMSMAC_OFILES := \
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phy/phytbl_n.o \
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phy/phy_qmath.o \
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dma.o \
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nicpci.o \
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brcms_trace_events.o
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MODULEPFX := brcmsmac
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@ -19,7 +19,6 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <defs.h>
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#include <chipcommon.h>
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@ -29,7 +28,6 @@
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#include "types.h"
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#include "pub.h"
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#include "pmu.h"
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#include "nicpci.h"
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#include "aiutils.h"
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/* slow_clk_ctl */
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@ -478,13 +476,6 @@ ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
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/* figure out buscore */
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sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
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/* fixup necessary chip/core configurations */
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if (!sii->pch) {
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sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
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if (sii->pch == NULL)
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return false;
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}
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return true;
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}
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@ -565,9 +556,6 @@ static struct si_info *ai_doattach(struct si_info *sii,
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return sii;
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exit:
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if (sii->pch)
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pcicore_deinit(sii->pch);
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sii->pch = NULL;
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return NULL;
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}
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@ -606,10 +594,6 @@ void ai_detach(struct si_pub *sih)
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if (sii == NULL)
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return;
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if (sii->pch)
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pcicore_deinit(sii->pch);
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sii->pch = NULL;
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kfree(sii);
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}
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@ -168,7 +168,6 @@ struct si_info {
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struct si_pub pub; /* back plane public state (must be first) */
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struct bcma_bus *icbus; /* handle to soc interconnect bus */
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struct pci_dev *pcibus; /* handle to pci bus */
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struct pcicore_info *pch; /* PCI/E core handle */
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struct bcma_device *buscore;
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u32 chipst; /* chip status */
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@ -25,7 +25,6 @@
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#include <linux/bcma/bcma.h>
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#include <net/mac80211.h>
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#include <defs.h>
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#include "nicpci.h"
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#include "phy/phy_int.h"
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#include "d11.h"
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#include "channel.h"
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@ -1,241 +0,0 @@
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/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <defs.h>
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#include <soc.h>
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#include <chipcommon.h>
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#include "aiutils.h"
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#include "pub.h"
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#include "nicpci.h"
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/* SPROM offsets */
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#define SRSH_ASPM_OFFSET 4 /* word 4 */
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#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
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#define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */
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#define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */
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#define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */
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#define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
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#define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
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#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
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#define SRSH_BD_OFFSET 6 /* word 6 */
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/* chipcontrol */
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#define CHIPCTRL_4321_PLL_DOWN 0x800000/* serdes PLL down override */
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/* MDIO control */
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#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
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#define MDIOCTL_DIVISOR_VAL 0x2
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#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
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#define MDIOCTL_ACCESS_DONE 0x100 /* Transaction complete */
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/* MDIO Data */
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#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
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#define MDIODATA_TA 0x00020000 /* Turnaround */
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#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
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#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
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#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
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#define MDIODATA_DEVADDR_MASK 0x0f800000
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/* Physmedia devaddr Mask */
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/* MDIO Data for older revisions < 10 */
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#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift */
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#define MDIODATA_REGADDR_MASK_OLD 0x003c0000
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/* Regaddr Mask */
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#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift */
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#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000
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/* Physmedia devaddr Mask */
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/* Transactions flags */
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#define MDIODATA_WRITE 0x10000000
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#define MDIODATA_READ 0x20000000
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#define MDIODATA_START 0x40000000
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#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
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#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
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/* serdes regs (rev < 10) */
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#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
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#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
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#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
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/* SERDES RX registers */
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#define SERDES_RX_CTRL 1 /* Rx cntrl */
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#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
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#define SERDES_RX_CDR 6 /* CDR */
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#define SERDES_RX_CDRBW 7 /* CDR BW */
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/* SERDES RX control register */
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#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
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#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
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/* SERDES PLL registers */
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#define SERDES_PLL_CTRL 1 /* PLL control reg */
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#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
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/* Linkcontrol reg offset in PCIE Cap */
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#define PCIE_CAP_LINKCTRL_OFFSET 16 /* offset in pcie cap */
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#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
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#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
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#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
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#define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */
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#define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */
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#define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */
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#define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */
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/* Power management threshold */
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#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
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#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
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#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
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#define PCIE_ASPMTIMER_EXTEND 0x01000000
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/* > rev7:
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* enable extend ASPM timer
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*/
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/* different register spaces to access thru pcie indirect access */
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#define PCIE_CONFIGREGS 1 /* Access to config space */
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#define PCIE_PCIEREGS 2 /* Access to pcie registers */
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/* PCIE protocol PHY diagnostic registers */
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#define PCIE_PLP_STATUSREG 0x204 /* Status */
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/* Status reg PCIE_PLP_STATUSREG */
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#define PCIE_PLP_POLARITYINV_STAT 0x10
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/* PCIE protocol DLLP diagnostic registers */
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#define PCIE_DLLP_LCREG 0x100 /* Link Control */
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#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
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/* PCIE protocol TLP diagnostic registers */
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#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
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/* Sonics to PCI translation types */
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#define SBTOPCI_PREF 0x4 /* prefetch enable */
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#define SBTOPCI_BURST 0x8 /* burst enable */
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#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
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#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
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/* PCI core index in SROM shadow area */
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#define SRSH_PI_OFFSET 0 /* first word */
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#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
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#define SRSH_PI_SHIFT 12 /* bit 15:12 */
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#define PCIREGOFFS(field) offsetof(struct sbpciregs, field)
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#define PCIEREGOFFS(field) offsetof(struct sbpcieregs, field)
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/* Sonics side: PCI core and host control registers */
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struct sbpciregs {
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u32 control; /* PCI control */
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u32 PAD[3];
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u32 arbcontrol; /* PCI arbiter control */
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u32 clkrun; /* Clkrun Control (>=rev11) */
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u32 PAD[2];
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u32 intstatus; /* Interrupt status */
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u32 intmask; /* Interrupt mask */
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u32 sbtopcimailbox; /* Sonics to PCI mailbox */
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u32 PAD[9];
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u32 bcastaddr; /* Sonics broadcast address */
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u32 bcastdata; /* Sonics broadcast data */
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u32 PAD[2];
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u32 gpioin; /* ro: gpio input (>=rev2) */
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u32 gpioout; /* rw: gpio output (>=rev2) */
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u32 gpioouten; /* rw: gpio output enable (>= rev2) */
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u32 gpiocontrol; /* rw: gpio control (>= rev2) */
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u32 PAD[36];
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u32 sbtopci0; /* Sonics to PCI translation 0 */
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u32 sbtopci1; /* Sonics to PCI translation 1 */
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u32 sbtopci2; /* Sonics to PCI translation 2 */
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u32 PAD[189];
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u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
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u16 sprom[36]; /* SPROM shadow Area */
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u32 PAD[46];
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};
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/* SB side: PCIE core and host control registers */
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struct sbpcieregs {
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u32 control; /* host mode only */
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u32 PAD[2];
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u32 biststatus; /* bist Status: 0x00C */
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u32 gpiosel; /* PCIE gpio sel: 0x010 */
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u32 gpioouten; /* PCIE gpio outen: 0x14 */
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u32 PAD[2];
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u32 intstatus; /* Interrupt status: 0x20 */
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u32 intmask; /* Interrupt mask: 0x24 */
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u32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
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u32 PAD[53];
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u32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
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u32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
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u32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
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u32 PAD[5];
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/* pcie core supports in direct access to config space */
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u32 configaddr; /* pcie config space access: Address field: 0x120 */
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u32 configdata; /* pcie config space access: Data field: 0x124 */
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/* mdio access to serdes */
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u32 mdiocontrol; /* controls the mdio access: 0x128 */
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u32 mdiodata; /* Data to the mdio access: 0x12c */
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/* pcie protocol phy/dllp/tlp register indirect access mechanism */
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u32 pcieindaddr; /* indirect access to
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* the internal register: 0x130
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*/
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u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
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u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
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u32 PAD[177];
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u32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
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u16 sprom[64]; /* SPROM shadow Area */
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};
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struct pcicore_info {
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struct bcma_device *core;
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struct si_pub *sih; /* System interconnect handle */
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struct pci_dev *dev;
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u8 pmecap_offset; /* PM Capability offset in the config space */
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bool pmecap; /* Capable of generating PME */
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};
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/* Initialize the PCI core.
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* It's caller's responsibility to make sure that this is done only once
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*/
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struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
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{
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struct pcicore_info *pi;
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/* alloc struct pcicore_info */
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pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
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if (pi == NULL)
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return NULL;
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pi->sih = sih;
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pi->dev = core->bus->host_pci;
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pi->core = core;
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return pi;
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}
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void pcicore_deinit(struct pcicore_info *pch)
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{
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kfree(pch);
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}
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@ -1,70 +0,0 @@
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/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BRCM_NICPCI_H_
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#define _BRCM_NICPCI_H_
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#include "types.h"
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/* PCI configuration address space size */
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#define PCI_SZPCR 256
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/* Brcm PCI configuration registers */
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/* backplane address space accessed by BAR0 */
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#define PCI_BAR0_WIN 0x80
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/* sprom property control */
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#define PCI_SPROM_CONTROL 0x88
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/* mask of PCI and other cores interrupts */
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#define PCI_INT_MASK 0x94
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/* backplane core interrupt mask bits offset */
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#define PCI_SBIM_SHIFT 8
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/* backplane address space accessed by second 4KB of BAR0 */
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#define PCI_BAR0_WIN2 0xac
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/* pci config space gpio input (>=rev3) */
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#define PCI_GPIO_IN 0xb0
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/* pci config space gpio output (>=rev3) */
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#define PCI_GPIO_OUT 0xb4
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/* pci config space gpio output enable (>=rev3) */
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#define PCI_GPIO_OUTEN 0xb8
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/* bar0 + 4K accesses external sprom */
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#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
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/* bar0 + 6K accesses pci core registers */
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#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
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/*
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* pci core SB registers are at the end of the
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* 8KB window, so their address is the "regular"
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* address plus 4K
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*/
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#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
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/* bar0 window size Match with corerev 13 */
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#define PCI_BAR0_WINSZ (16 * 1024)
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/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
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/* bar0 + 8K accesses pci/pcie core registers */
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#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
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/* bar0 + 12K accesses chipc core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
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struct sbpciregs;
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struct sbpcieregs;
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extern struct pcicore_info *pcicore_init(struct si_pub *sih,
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struct bcma_device *core);
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extern void pcicore_deinit(struct pcicore_info *pch);
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extern void pcicore_up(struct pcicore_info *pch, int state);
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extern void pcicore_down(struct pcicore_info *pch, int state);
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#endif /* _BRCM_NICPCI_H_ */
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