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https://github.com/torvalds/linux
synced 2024-09-06 09:51:23 +00:00
ALSA: emu10k1: fixup DSP defines
Firstly, fix the distribution between public and private headers. Otherwise, some of the already public macros wouldn't actually work, and the SNDRV_EMU10K1_IOCTL_DBG_READ result for Audigy would be useless. Secondly, add condition code registers for Audigy. These are just aliases for selected constant registers, and thus are generation- specific. At least A_CC_REG_ZERO is actually correct ... Finally, shuffle around some defines to more logical places while at it, and fix up some more comments. Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de> Link: https://lore.kernel.org/r/20230422161021.1143903-7-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Oswald Buddenhagen
Takashi Iwai
parent
145ec1fd00
commit
2696d5a3b0
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@ -704,18 +704,15 @@
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#define GPSCS 0x51 /* General Purpose SPDIF channel status register */
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// Corresponding EMU10K1_DBG_* constants are in the public header
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#define DBG 0x52
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#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
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#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
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#define A_DBG 0x53
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#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
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#define A_DBG_ZC 0x40000000 /* zero tram counter */
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#define A_DBG_STEP_ADDR 0x000003ff
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#define A_DBG_SATURATION_OCCURED 0x20000000
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#define A_DBG_SATURATION_ADDR 0x0ffc0000
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// Corresponding A_DBG_* constants are in the public header
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#define A_DBG 0x53
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// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
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#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
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@ -908,45 +905,14 @@
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#define A_FXRT_CHANNELD 0x3f000000
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/* 0x7f: Not used */
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/* Each FX general purpose register is 32 bits in length, all bits are used */
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#define FXGPREGBASE 0x100 /* FX general purpose registers base */
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#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
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#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
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#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
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/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
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/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
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/* locations are for external TRAM. */
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#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
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#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
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/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
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#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
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#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
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#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
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#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
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#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
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#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
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#define MICROCODEBASE 0x400 /* Microcode data base address */
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/* The public header defines the GPR and TRAM base addresses that
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* are valid for _both_ CPU and DSP addressing. */
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/* Each DSP microcode instruction is mapped into 2 doublewords */
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/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
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#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
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#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
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#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
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#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
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#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
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/* Audigy Soundcard have a different instruction format */
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#define MICROCODEBASE 0x400 /* Microcode data base address */
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#define A_MICROCODEBASE 0x600
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#define A_LOWORD_OPY_MASK 0x000007ff
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#define A_LOWORD_OPX_MASK 0x007ff000
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#define A_HIWORD_OPCODE_MASK 0x0f000000
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#define A_HIWORD_RESULT_MASK 0x007ff000
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#define A_HIWORD_OPA_MASK 0x000007ff
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/************************************************************************************************/
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@ -43,6 +43,19 @@
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#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
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#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
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#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
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#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
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#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
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#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
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#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
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/* Audigy Soundcards have a different instruction format */
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#define A_LOWORD_OPX_MASK 0x007ff000
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#define A_LOWORD_OPY_MASK 0x000007ff
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#define A_HIWORD_OPCODE_MASK 0x0f000000
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#define A_HIWORD_RESULT_MASK 0x007ff000
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#define A_HIWORD_OPA_MASK 0x000007ff
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/* GPRs */
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#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
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#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
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@ -50,6 +63,16 @@
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#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
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/* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
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#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
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#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
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#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
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#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
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#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
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#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" */
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#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_01 - _0F" */
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#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x1f "EMU32_IN_00 - _1F" - Only when .device = 0x0008 */
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#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x1f "EMU32_OUT_00 - _1F" - Only when .device = 0x0008 */
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#define C_00000000 0x40
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#define C_00000001 0x41
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#define C_00000002 0x42
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@ -78,12 +101,66 @@
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#define GPR_NOISE1 0x59 /* noise source */
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#define GPR_IRQ 0x5a /* IRQ register */
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#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
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/* Audigy constants */
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#define A_C_00000000 0xc0
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#define A_C_00000001 0xc1
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#define A_C_00000002 0xc2
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#define A_C_00000003 0xc3
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#define A_C_00000004 0xc4
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#define A_C_00000008 0xc5
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#define A_C_00000010 0xc6
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#define A_C_00000020 0xc7
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#define A_C_00000100 0xc8
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#define A_C_00010000 0xc9
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#define A_C_00000800 0xca
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#define A_C_10000000 0xcb
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#define A_C_20000000 0xcc
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#define A_C_40000000 0xcd
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#define A_C_80000000 0xce
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#define A_C_7fffffff 0xcf
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#define A_C_ffffffff 0xd0
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#define A_C_fffffffe 0xd1
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#define A_C_c0000000 0xd2
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#define A_C_4f1bbcdc 0xd3
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#define A_C_5a7ef9db 0xd4
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#define A_C_00100000 0xd5
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#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
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#define A_GPR_COND 0xd7 /* CCR, condition register */
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#define A_GPR_NOISE0 0xd8 /* noise source */
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#define A_GPR_NOISE1 0xd9 /* noise source */
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#define A_GPR_IRQ 0xda /* IRQ register */
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#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
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#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
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/* Each FX general purpose register is 32 bits in length, all bits are used */
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#define FXGPREGBASE 0x100 /* FX general purpose registers base */
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#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
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#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
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#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
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/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
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/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
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/* locations are for external TRAM. */
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#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
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#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
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/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
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#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
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#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
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#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
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#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
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#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
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#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
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#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
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#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
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#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
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#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
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#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
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#define A_GPR(x) (A_FXGPREGBASE + (x))
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#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
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#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
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#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
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@ -91,17 +168,6 @@
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#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
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#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
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#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
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#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
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#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
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#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
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#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
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#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
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#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
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#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
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#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
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#define A_GPR(x) (A_FXGPREGBASE + (x))
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/* cc_reg constants */
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#define CC_REG_NORMALIZED C_00000001
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#define CC_REG_BORROW C_00000002
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@ -110,6 +176,13 @@
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#define CC_REG_SATURATE C_00000010
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#define CC_REG_NONZERO C_00000100
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#define A_CC_REG_NORMALIZED A_C_00000001
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#define A_CC_REG_BORROW A_C_00000002
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#define A_CC_REG_MINUS A_C_00000004
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#define A_CC_REG_ZERO A_C_00000008
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#define A_CC_REG_SATURATE A_C_00000010
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#define A_CC_REG_NONZERO A_C_00000100
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/* FX buses */
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// These are arbitrary mappings; our DSP code simply expects
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// the config files to route the channels this way.
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@ -203,38 +276,7 @@
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#define A_EXTOUT_ADC_CAP_R 0x17 /* right */
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#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
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/* Audigy constants */
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#define A_C_00000000 0xc0
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#define A_C_00000001 0xc1
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#define A_C_00000002 0xc2
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#define A_C_00000003 0xc3
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#define A_C_00000004 0xc4
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#define A_C_00000008 0xc5
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#define A_C_00000010 0xc6
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#define A_C_00000020 0xc7
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#define A_C_00000100 0xc8
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#define A_C_00010000 0xc9
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#define A_C_00000800 0xca
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#define A_C_10000000 0xcb
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#define A_C_20000000 0xcc
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#define A_C_40000000 0xcd
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#define A_C_80000000 0xce
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#define A_C_7fffffff 0xcf
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#define A_C_ffffffff 0xd0
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#define A_C_fffffffe 0xd1
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#define A_C_c0000000 0xd2
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#define A_C_4f1bbcdc 0xd3
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#define A_C_5a7ef9db 0xd4
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#define A_C_00100000 0xd5
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#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
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#define A_GPR_COND 0xd7 /* CCR, condition register */
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#define A_GPR_NOISE0 0xd8 /* noise source */
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#define A_GPR_NOISE1 0xd9 /* noise source */
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#define A_GPR_IRQ 0xda /* IRQ register */
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#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
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#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
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/* definitions for debug register */
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/* Definitions for debug register. Note that these are for emu10k1 ONLY. */
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#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
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#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
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#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
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@ -243,14 +285,14 @@
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#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
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#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
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/* tank memory address line */
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#ifndef __KERNEL__
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#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
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#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
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#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
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#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
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#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
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#endif
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/* Definitions for emu10k2 debug register. */
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#define A_DBG_ZC 0x40000000 /* zero tram counter */
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#define A_DBG_SATURATION_OCCURED 0x20000000
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#define A_DBG_SATURATION_ADDR 0x0ffc0000
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#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
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#define A_DBG_STEP 0x00010000
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#define A_DBG_CONDITION_CODE 0x0000f800
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#define A_DBG_STEP_ADDR 0x000003ff
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struct snd_emu10k1_fx8010_info {
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unsigned int internal_tram_size; /* in samples */
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