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Devicetree fixes for v5.6:
- Fix incorrect $id paths in schemas - 2 fixes for Intel LGM SoC binding schemas -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl46iQoQHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhw1WAD/9vM7kmCWN1T3czpkX2ZOILTY8maVxOR512 5t4RiFqxbU3a7fvb7WZqzlH1KbunlYOvTsWhMOddIVT0YrujicjjRQ6v1OjL078m uqgJ8J6coC1o2iAGW+Jv3jzcQthdUWWURsj78UrdeftYemX/MMDHkKXiVjg+s9L0 n/wHEaxXG3KT1MjA2meA0SSLUwBqEy8wukPON6t12LSsVW6GVJYlEYXBok9rD3pC Wl2zW7Iyza+223oeoU7aUh8ePNdCiHoy3RKg/phx6CsqngMzFug0+vxPVmTSR/as QVEDUBiyqRLtOzNyDhpiNUWMNwXaZ2X/romPg4rv2A0mqAdRe0H8IO08ObsnMro9 hBOX07Yfr2h88QGavktOpGrFJmvWo1f+EvjyN9gm+r6pTT+xVLmjRFbnC8RXcJnq id8QzV7KTtH1r/W8iDpEMCCElAfoQ8poKnzfXSKEiWk8Bd8em62h/BRAF7362AEr SBwcqqqBEwF2gEZuiYBPTPRI2/Vc4+f7StK8qDnJlDxqg9DSExLg+bpyH4L1zoeA 4DQlrXFiTyMawc6DC+Fscc/CtMivvX91DYox3biU4d2mYfVrWvn/1ZuDRXzmUNvn agh63kuXKbIXirTTP1vhW1q22m3ishlGtiffazVrGV9MtTSNG5DqCeQ0ukB35GAj ucFd7PHM5A== =ypMI -----END PGP SIGNATURE----- Merge tag 'devicetree-fixes-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree fixes from Rob Herring: - Fix incorrect $id paths in schemas - Two fixes for Intel LGM SoC binding schemas * tag 'devicetree-fixes-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: Fix paths in schema $id fields dt-bindings: PCI: intel: Fix dt_binding_check compilation failure dt-bindings: phy: Fix errors in intel,lgm-emmc-phy example
This commit is contained in:
Linus Torvalds
commit
2634744bf3
24 changed files with 26 additions and 26 deletions
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml#
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$id: http://devicetree.org/schemas/arm/fsl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX Platforms Device Tree Bindings
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/arm/qcom.yaml#
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$id: http://devicetree.org/schemas/arm/qcom.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: QCOM device tree bindings
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#
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$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain BM1880 Clock Controller
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/fsl,sai-clock.yaml#
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$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale SAI bitclock-as-a-clock binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
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$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Nano Clock Control Module Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/imx8mp-clock.yaml#
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$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Plus Clock Control Module Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml#
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$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Milbeaut SoCs Clock Controller Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,gcc.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller Binding
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,mmcc.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Multimedia Clock & Reset Controller Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,rpmhcc.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. RPMh Clocks Bindings
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,videocc.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Video Clock & Reset Controller Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/st,stm32mp1-rcc.yaml#
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$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Reset Clock Controller Binding
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
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$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Versal clock controller
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/hwmon/adi,ltc2947.yaml#
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$id: http://devicetree.org/schemas/hwmon/adi,ltc2947.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices LTC2947 high precision power and energy monitor
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@ -2,7 +2,7 @@
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# Copyright 2019 Analog Devices Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/iio/adc/adi,ad7124.yaml#
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$id: http://devicetree.org/schemas/iio/adc/adi,ad7124.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AD7124 ADC device driver
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@ -2,7 +2,7 @@
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# Copyright 2019 Analog Devices Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/iio/adc/adi,ad7192.yaml#
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$id: http://devicetree.org/schemas/iio/adc/adi,ad7192.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AD7192 ADC device driver
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@ -2,7 +2,7 @@
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# Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com>
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/bindings/iio/adc/microchip,mcp3911.yaml#"
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$id: "http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip MCP3911 Dual channel analog front end (ADC)
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/st,stm32-dfsdm-adc.yaml#
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$id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 DFSDM ADC device driver
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@ -2,7 +2,7 @@
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# Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com>
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/bindings/iio/dac/lltc,ltc1660.yaml#"
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$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Linear Technology Micropower octal 8-Bit and 10-Bit DACs
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/input/gpio-vibrator.yaml#
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$id: http://devicetree.org/schemas/input/gpio-vibrator.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: GPIO vibrator
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@ -107,7 +107,6 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/intel,lgm-clk.h>
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pcie10: pcie@d0e00000 {
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compatible = "intel,lgm-pcie", "snps,dw-pcie";
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device_type = "pci";
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@ -120,7 +119,6 @@ examples:
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linux,pci-domain = <0>;
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max-link-speed = <4>;
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bus-range = <0x00 0x08>;
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interrupt-parent = <&ioapic1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &ioapic1 27 1>,
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<0 0 0 4 &ioapic1 30 1>;
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ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
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resets = <&rcu0 0x50 0>;
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clocks = <&cgu0 LGM_GCLK_PCIE10>;
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clocks = <&cgu0 120>;
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phys = <&cb0phy0>;
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phy-names = "pcie";
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reset-assert-ms = <500>;
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sysconf: chiptop@e0200000 {
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compatible = "intel,lgm-syscon", "syscon";
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reg = <0xe0200000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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emmc-phy: emmc-phy@a8 {
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emmc_phy: emmc-phy@a8 {
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compatible = "intel,lgm-emmc-phy";
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reg = <0x00a8 0x10>;
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clocks = <&emmc>;
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