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phy: qcom: sgmii-eth: move PCS registers to separate header
Follow the example of the rest of the QMP PHY drivers and move SGMII PCS registers to a separate header file. Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-8-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
parent
df71879bec
commit
25ee21fc97
20
drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
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20
drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_SGMII_H_
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#define QCOM_PHY_QMP_PCS_SGMII_H_
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#define QPHY_PCS_PHY_START 0x000
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#define QPHY_PCS_POWER_DOWN_CONTROL 0x004
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#define QPHY_PCS_SW_RESET 0x008
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#define QPHY_PCS_LINE_RESET_TIME 0x00c
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#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
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#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
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#define QPHY_PCS_PCS_READY_STATUS 0x094
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#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
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#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
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#define QPHY_PCS_SGMII_MISC_CTRL8 0x118
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#endif
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@ -11,6 +11,7 @@
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "phy-qcom-qmp-pcs-sgmii.h"
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#include "phy-qcom-qmp-qserdes-com-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5.h"
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@ -19,17 +20,6 @@
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#define QSERDES_TX 0x400
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#define QSERDES_PCS 0xc00
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#define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0)
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#define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4)
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#define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8)
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#define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc)
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#define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20)
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#define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28)
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#define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8)
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#define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc)
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#define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118)
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#define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94)
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#define QSERDES_COM_C_READY BIT(0)
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#define QSERDES_PCS_READY BIT(0)
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#define QSERDES_PCS_SGMIIPHY_READY BIT(7)
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@ -43,8 +33,8 @@ struct qcom_dwmac_sgmii_phy_data {
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static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap)
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{
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regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);
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regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
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regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
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regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
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@ -118,21 +108,21 @@ static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap)
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regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);
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regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);
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regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);
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regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
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regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
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regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83);
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regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
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regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C);
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regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
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regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
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}
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static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap)
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{
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regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);
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regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
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regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
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regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
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@ -206,15 +196,15 @@ static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap)
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regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);
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regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);
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regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);
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regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
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regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
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regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83);
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regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
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regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C);
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regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
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regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01);
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regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
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}
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static inline int
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@ -251,14 +241,14 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy)
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}
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if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
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QSERDES_PCS_PCS_READY_STATUS,
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QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS,
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QSERDES_PCS_READY)) {
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dev_err(dev, "PCS_READY timed-out");
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return -ETIMEDOUT;
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}
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if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
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QSERDES_PCS_PCS_READY_STATUS,
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QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS,
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QSERDES_PCS_SGMIIPHY_READY)) {
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dev_err(dev, "SGMIIPHY_READY timed-out");
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return -ETIMEDOUT;
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@ -285,11 +275,11 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy)
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{
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struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
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regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
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regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01);
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regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
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regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
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udelay(100);
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regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00);
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regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01);
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regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
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regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
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clk_disable_unprepare(data->refclk);
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