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drm/i915/dsi: Enable dithering for 6 bpc panels
The display engine has 2 dithering enable bits which both need to be set for dithering to happen, 1 in the PIPECONF register which is taken care of by i9xx_set_pipeconf() and a second bit at the encoder level. The dsi code was not setting the encoder level dithering enable bit causing dithering to be disabled, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181201113148.23184-2-hdegoede@redhat.com
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@ -678,6 +678,10 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
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LANE_CONFIGURATION_DUAL_LINK_B :
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LANE_CONFIGURATION_DUAL_LINK_A;
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}
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if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
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temp |= DITHERING_ENABLE;
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/* assert ip_tg_enable signal */
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I915_WRITE(port_ctrl, temp | DPI_ENABLE);
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POSTING_READ(port_ctrl);
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