mirror of
https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
MIPS: Malta: Make use of generic CM support
Remove the Malta-specific CM probe code and instead make use of the newly added generic CM code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6364/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
0ee958e102
commit
237036de65
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@ -868,6 +868,7 @@ config CEVT_R4K
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bool
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bool
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config CEVT_GIC
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config CEVT_GIC
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select MIPS_CM
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bool
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bool
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config CEVT_SB1250
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config CEVT_SB1250
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@ -886,6 +887,7 @@ config CSRC_R4K
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bool
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bool
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config CSRC_GIC
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config CSRC_GIC
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select MIPS_CM
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bool
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bool
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config CSRC_SB1250
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config CSRC_SB1250
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@ -1030,6 +1032,7 @@ config IRQ_GT641XX
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bool
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bool
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config IRQ_GIC
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config IRQ_GIC
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select MIPS_CM
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bool
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bool
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config PCI_GT64XXX_PCI0
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config PCI_GT64XXX_PCI0
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@ -13,6 +13,8 @@
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <asm/mips-cm.h>
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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#include <linux/cpumask.h>
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#include <linux/cpumask.h>
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@ -79,6 +81,9 @@ static inline int register_cmp_smp_ops(void)
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#ifdef CONFIG_MIPS_CMP
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#ifdef CONFIG_MIPS_CMP
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extern struct plat_smp_ops cmp_smp_ops;
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extern struct plat_smp_ops cmp_smp_ops;
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if (!mips_cm_present())
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return -ENODEV;
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register_smp_ops(&cmp_smp_ops);
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register_smp_ops(&cmp_smp_ops);
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return 0;
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return 0;
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@ -20,7 +20,7 @@
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#include <asm/smp-ops.h>
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#include <asm/smp-ops.h>
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#include <asm/traps.h>
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#include <asm/traps.h>
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#include <asm/fw/fw.h>
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#include <asm/fw/fw.h>
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#include <asm/gcmpregs.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/malta.h>
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@ -276,10 +276,10 @@ void __init prom_init(void)
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console_config();
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console_config();
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#endif
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#endif
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/* Early detection of CMP support */
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/* Early detection of CMP support */
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if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ))
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mips_cm_probe();
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if (!register_cmp_smp_ops())
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return;
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if (!register_cmp_smp_ops())
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return;
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if (!register_vsmp_smp_ops())
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if (!register_vsmp_smp_ops())
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return;
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return;
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@ -26,6 +26,7 @@
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#include <asm/i8259.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq_regs.h>
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#include <asm/irq_regs.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/gt64120.h>
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#include <asm/gt64120.h>
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@ -33,13 +34,10 @@
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/msc01_ic.h>
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#include <asm/msc01_ic.h>
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#include <asm/gic.h>
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#include <asm/gic.h>
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#include <asm/gcmpregs.h>
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#include <asm/setup.h>
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#include <asm/setup.h>
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#include <asm/rtlx.h>
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#include <asm/rtlx.h>
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int gcmp_present = -1;
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static unsigned long _msc01_biu_base;
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static unsigned long _msc01_biu_base;
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static unsigned long _gcmp_base;
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static unsigned int ipi_map[NR_CPUS];
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static unsigned int ipi_map[NR_CPUS];
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static DEFINE_RAW_SPINLOCK(mips_irq_lock);
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static DEFINE_RAW_SPINLOCK(mips_irq_lock);
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@ -418,48 +416,6 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
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};
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};
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#undef X
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#undef X
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/*
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* GCMP needs to be detected before any SMP initialisation
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*/
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int __init gcmp_probe(unsigned long addr, unsigned long size)
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{
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if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) &&
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(mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) {
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gcmp_present = 0;
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pr_debug("GCMP NOT present\n");
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return gcmp_present;
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}
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if (gcmp_present >= 0)
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return gcmp_present;
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_gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR,
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GCMP_ADDRSPACE_SZ);
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_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE,
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MSC01_BIU_ADDRSPACE_SZ);
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gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) ==
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GCMP_BASE_ADDR);
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if (gcmp_present)
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pr_debug("GCMP present\n");
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return gcmp_present;
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}
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/* Return the number of IOCU's present */
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int __init gcmp_niocu(void)
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{
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return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >>
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GCMP_GCB_GC_NUMIOCU_SHF) : 0;
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}
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/* Set GCMP region attributes */
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void __init gcmp_setregion(int region, unsigned long base,
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unsigned long mask, int type)
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{
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GCMPGCBn(CMxBASE, region) = base;
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GCMPGCBn(CMxMASK, region) = mask | type;
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}
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#if defined(CONFIG_MIPS_MT_SMP)
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#if defined(CONFIG_MIPS_MT_SMP)
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static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
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static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
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{
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{
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@ -496,8 +452,8 @@ void __init arch_init_irq(void)
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if (!cpu_has_veic)
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if (!cpu_has_veic)
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mips_cpu_irq_init();
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mips_cpu_irq_init();
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if (gcmp_present) {
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if (mips_cm_present()) {
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GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
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write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
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gic_present = 1;
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gic_present = 1;
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} else {
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} else {
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if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
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if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
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@ -584,7 +540,7 @@ void __init arch_init_irq(void)
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#endif
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#endif
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gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
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gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
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ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
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ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
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if (!gcmp_present) {
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if (!mips_cm_present()) {
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/* Enable the GIC */
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/* Enable the GIC */
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i = REG(_msc01_biu_base, MSC01_SC_CFG);
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i = REG(_msc01_biu_base, MSC01_SC_CFG);
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REG(_msc01_biu_base, MSC01_SC_CFG) =
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REG(_msc01_biu_base, MSC01_SC_CFG) =
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/* This duplicates the handling in do_be which seems wrong */
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/* This duplicates the handling in do_be which seems wrong */
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int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
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int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
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if (gcmp_present) {
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if (mips_cm_present()) {
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unsigned long cm_error = GCMPGCB(GCMEC);
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unsigned long cm_error = read_gcr_error_cause();
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unsigned long cm_addr = GCMPGCB(GCMEA);
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unsigned long cm_addr = read_gcr_error_addr();
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unsigned long cm_other = GCMPGCB(GCMEO);
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unsigned long cm_other = read_gcr_error_mult();
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unsigned long cause, ocause;
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unsigned long cause, ocause;
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char buf[256];
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char buf[256];
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cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
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cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK;
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if (cause != 0) {
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if (cause != 0) {
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cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
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cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
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if (cause < 16) {
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if (cause < 16) {
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unsigned long cca_bits = (cm_error >> 15) & 7;
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unsigned long cca_bits = (cm_error >> 15) & 7;
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unsigned long tr_bits = (cm_error >> 12) & 7;
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unsigned long tr_bits = (cm_error >> 12) & 7;
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mcmd[cmd_bits], sport_bits);
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mcmd[cmd_bits], sport_bits);
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}
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}
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ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
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ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >>
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GCMP_GCB_GMEO_ERROR_2ND_SHF;
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CM_GCR_ERROR_MULT_ERR2ND_SHF;
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pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
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pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
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causes[cause], buf);
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causes[cause], buf);
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pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
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pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
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/* reprime cause register */
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/* reprime cause register */
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GCMPGCB(GCMEC) = 0;
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write_gcr_error_cause(0);
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}
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}
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}
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}
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@ -26,12 +26,12 @@
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#include <linux/time.h>
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#include <linux/time.h>
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#include <asm/fw/fw.h>
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#include <asm/fw/fw.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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#include <asm/traps.h>
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#include <asm/traps.h>
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#include <asm/gcmpregs.h>
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#ifdef CONFIG_VT
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#ifdef CONFIG_VT
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#include <linux/console.h>
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#include <linux/console.h>
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#endif
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#endif
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@ -127,7 +127,7 @@ static int __init plat_enable_iocoherency(void)
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Enabled Bonito IOBC coherency\n");
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pr_info("Enabled Bonito IOBC coherency\n");
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}
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}
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} else if (gcmp_niocu() != 0) {
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} else if (mips_cm_numiocu() != 0) {
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/* Nothing special needs to be done to enable coherency */
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/* Nothing special needs to be done to enable coherency */
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pr_info("CMP IOCU detected\n");
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pr_info("CMP IOCU detected\n");
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if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
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if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
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@ -27,7 +27,7 @@
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#include <linux/init.h>
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#include <linux/init.h>
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#include <asm/gt64120.h>
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#include <asm/gt64120.h>
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#include <asm/gcmpregs.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/bonito64.h>
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#include <asm/mips-boards/bonito64.h>
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/mips-boards/msc01_pci.h>
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@ -201,11 +201,11 @@ void __init mips_pcibios_init(void)
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msc_mem_resource.start = start & mask;
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msc_mem_resource.start = start & mask;
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msc_mem_resource.end = (start & mask) | ~mask;
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msc_mem_resource.end = (start & mask) | ~mask;
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msc_controller.mem_offset = (start & mask) - (map & mask);
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msc_controller.mem_offset = (start & mask) - (map & mask);
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#ifdef CONFIG_MIPS_CMP
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if (mips_cm_numiocu()) {
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if (gcmp_niocu())
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write_gcr_reg0_base(start);
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gcmp_setregion(0, start, mask,
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write_gcr_reg0_mask(mask |
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GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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#endif
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}
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MSC_READ(MSC01_PCI_SC2PIOBASL, start);
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MSC_READ(MSC01_PCI_SC2PIOBASL, start);
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MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
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MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
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MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
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MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
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msc_io_resource.end = (map & mask) | ~mask;
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msc_io_resource.end = (map & mask) | ~mask;
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msc_controller.io_offset = 0;
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msc_controller.io_offset = 0;
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ioport_resource.end = ~mask;
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ioport_resource.end = ~mask;
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#ifdef CONFIG_MIPS_CMP
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if (mips_cm_numiocu()) {
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if (gcmp_niocu())
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write_gcr_reg1_base(start);
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gcmp_setregion(1, start, mask,
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write_gcr_reg1_mask(mask |
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GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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#endif
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}
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/* If ranges overlap I/O takes precedence. */
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/* If ranges overlap I/O takes precedence. */
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start = start & mask;
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start = start & mask;
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end = start | ~mask;
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end = start | ~mask;
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