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x86/sev: Add SEV-SNP host initialization support
The memory integrity guarantees of SEV-SNP are enforced through a new structure called the Reverse Map Table (RMP). The RMP is a single data structure shared across the system that contains one entry for every 4K page of DRAM that may be used by SEV-SNP VMs. The APM Volume 2 section on Secure Nested Paging (SEV-SNP) details a number of steps needed to detect/enable SEV-SNP and RMP table support on the host: - Detect SEV-SNP support based on CPUID bit - Initialize the RMP table memory reported by the RMP base/end MSR registers and configure IOMMU to be compatible with RMP access restrictions - Set the MtrrFixDramModEn bit in SYSCFG MSR - Set the SecureNestedPagingEn and VMPLEn bits in the SYSCFG MSR - Configure IOMMU RMP table entry format is non-architectural and it can vary by processor. It is defined by the PPR document for each respective CPU family. Restrict SNP support to CPU models/families which are compatible with the current RMP table entry format to guard against any undefined behavior when running on other system types. Future models/support will handle this through an architectural mechanism to allow for broader compatibility. SNP host code depends on CONFIG_KVM_AMD_SEV config flag which may be enabled even when CONFIG_AMD_MEM_ENCRYPT isn't set, so update the SNP-specific IOMMU helpers used here to rely on CONFIG_KVM_AMD_SEV instead of CONFIG_AMD_MEM_ENCRYPT. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Co-developed-by: Ashish Kalra <ashish.kalra@amd.com> Signed-off-by: Ashish Kalra <ashish.kalra@amd.com> Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Co-developed-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Co-developed-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Link: https://lore.kernel.org/r/20240126041126.1927228-5-michael.roth@amd.com
This commit is contained in:
parent
04d65a9dbb
commit
216d106c7f
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@ -28,5 +28,7 @@ obj-y += net/
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obj-$(CONFIG_KEXEC_FILE) += purgatory/
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obj-y += virt/svm/
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# for cleaning
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subdir- += boot tools
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@ -599,6 +599,8 @@
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#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
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#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
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#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
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#define MSR_AMD64_RMP_BASE 0xc0010132
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#define MSR_AMD64_RMP_END 0xc0010133
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/* SNP feature bits enabled by the hypervisor */
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#define MSR_AMD64_SNP_VTOM BIT_ULL(3)
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@ -710,6 +712,13 @@
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#define MSR_AMD64_SYSCFG 0xc0010010
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#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
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#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
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#define MSR_AMD64_SYSCFG_SNP_EN_BIT 24
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#define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT)
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#define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25
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#define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT)
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#define MSR_AMD64_SYSCFG_MFDM_BIT 19
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#define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT)
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#define MSR_K8_INT_PENDING_MSG 0xc0010055
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/* C1E active bits in int pending message */
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#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
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@ -243,4 +243,10 @@ static inline u64 snp_get_unsupported_features(u64 status) { return 0; }
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static inline u64 sev_get_status(void) { return 0; }
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#endif
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#ifdef CONFIG_KVM_AMD_SEV
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bool snp_probe_rmptable_info(void);
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#else
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static inline bool snp_probe_rmptable_info(void) { return false; }
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#endif
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#endif
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@ -20,6 +20,7 @@
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#include <asm/delay.h>
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#include <asm/debugreg.h>
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#include <asm/resctrl.h>
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#include <asm/sev.h>
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#ifdef CONFIG_X86_64
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# include <asm/mmconfig.h>
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@ -587,6 +588,21 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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break;
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}
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if (cpu_has(c, X86_FEATURE_SEV_SNP)) {
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/*
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* RMP table entry format is not architectural and it can vary by processor
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* and is defined by the per-processor PPR. Restrict SNP support on the
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* known CPU model and family for which the RMP table entry format is
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* currently defined for.
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*/
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if (!boot_cpu_has(X86_FEATURE_ZEN3) &&
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!boot_cpu_has(X86_FEATURE_ZEN4) &&
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!boot_cpu_has(X86_FEATURE_ZEN5))
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setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
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else if (!snp_probe_rmptable_info())
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setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
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}
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return;
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warn:
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3
arch/x86/virt/svm/Makefile
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3
arch/x86/virt/svm/Makefile
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_KVM_AMD_SEV) += sev.o
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216
arch/x86/virt/svm/sev.c
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216
arch/x86/virt/svm/sev.c
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@ -0,0 +1,216 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD SVM-SEV Host Support.
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*
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* Copyright (C) 2023 Advanced Micro Devices, Inc.
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*
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* Author: Ashish Kalra <ashish.kalra@amd.com>
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*
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*/
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#include <linux/cc_platform.h>
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#include <linux/printk.h>
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#include <linux/mm_types.h>
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#include <linux/set_memory.h>
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#include <linux/memblock.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/cpumask.h>
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#include <linux/iommu.h>
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#include <linux/amd-iommu.h>
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#include <asm/sev.h>
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#include <asm/processor.h>
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#include <asm/setup.h>
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#include <asm/svm.h>
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#include <asm/smp.h>
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#include <asm/cpu.h>
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#include <asm/apic.h>
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#include <asm/cpuid.h>
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#include <asm/cmdline.h>
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#include <asm/iommu.h>
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/*
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* The RMP entry format is not architectural. The format is defined in PPR
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* Family 19h Model 01h, Rev B1 processor.
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*/
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struct rmpentry {
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u64 assigned : 1,
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pagesize : 1,
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immutable : 1,
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rsvd1 : 9,
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gpa : 39,
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asid : 10,
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vmsa : 1,
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validated : 1,
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rsvd2 : 1;
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u64 rsvd3;
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} __packed;
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/*
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* The first 16KB from the RMP_BASE is used by the processor for the
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* bookkeeping, the range needs to be added during the RMP entry lookup.
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*/
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#define RMPTABLE_CPU_BOOKKEEPING_SZ 0x4000
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static u64 probed_rmp_base, probed_rmp_size;
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static struct rmpentry *rmptable __ro_after_init;
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static u64 rmptable_max_pfn __ro_after_init;
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#undef pr_fmt
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#define pr_fmt(fmt) "SEV-SNP: " fmt
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static int __mfd_enable(unsigned int cpu)
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{
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u64 val;
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if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP))
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return 0;
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rdmsrl(MSR_AMD64_SYSCFG, val);
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val |= MSR_AMD64_SYSCFG_MFDM;
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wrmsrl(MSR_AMD64_SYSCFG, val);
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return 0;
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}
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static __init void mfd_enable(void *arg)
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{
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__mfd_enable(smp_processor_id());
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}
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static int __snp_enable(unsigned int cpu)
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{
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u64 val;
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if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP))
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return 0;
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rdmsrl(MSR_AMD64_SYSCFG, val);
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val |= MSR_AMD64_SYSCFG_SNP_EN;
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val |= MSR_AMD64_SYSCFG_SNP_VMPL_EN;
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wrmsrl(MSR_AMD64_SYSCFG, val);
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return 0;
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}
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static __init void snp_enable(void *arg)
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{
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__snp_enable(smp_processor_id());
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}
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#define RMP_ADDR_MASK GENMASK_ULL(51, 13)
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bool snp_probe_rmptable_info(void)
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{
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u64 max_rmp_pfn, calc_rmp_sz, rmp_sz, rmp_base, rmp_end;
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rdmsrl(MSR_AMD64_RMP_BASE, rmp_base);
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rdmsrl(MSR_AMD64_RMP_END, rmp_end);
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if (!(rmp_base & RMP_ADDR_MASK) || !(rmp_end & RMP_ADDR_MASK)) {
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pr_err("Memory for the RMP table has not been reserved by BIOS\n");
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return false;
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}
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if (rmp_base > rmp_end) {
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pr_err("RMP configuration not valid: base=%#llx, end=%#llx\n", rmp_base, rmp_end);
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return false;
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}
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rmp_sz = rmp_end - rmp_base + 1;
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/*
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* Calculate the amount the memory that must be reserved by the BIOS to
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* address the whole RAM, including the bookkeeping area. The RMP itself
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* must also be covered.
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*/
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max_rmp_pfn = max_pfn;
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if (PHYS_PFN(rmp_end) > max_pfn)
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max_rmp_pfn = PHYS_PFN(rmp_end);
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calc_rmp_sz = (max_rmp_pfn << 4) + RMPTABLE_CPU_BOOKKEEPING_SZ;
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if (calc_rmp_sz > rmp_sz) {
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pr_err("Memory reserved for the RMP table does not cover full system RAM (expected 0x%llx got 0x%llx)\n",
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calc_rmp_sz, rmp_sz);
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return false;
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}
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probed_rmp_base = rmp_base;
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probed_rmp_size = rmp_sz;
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pr_info("RMP table physical range [0x%016llx - 0x%016llx]\n",
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probed_rmp_base, probed_rmp_base + probed_rmp_size - 1);
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return true;
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}
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/*
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* Do the necessary preparations which are verified by the firmware as
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* described in the SNP_INIT_EX firmware command description in the SNP
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* firmware ABI spec.
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*/
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static int __init snp_rmptable_init(void)
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{
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void *rmptable_start;
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u64 rmptable_size;
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u64 val;
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if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP))
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return 0;
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if (!amd_iommu_snp_en)
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return 0;
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if (!probed_rmp_size)
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goto nosnp;
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rmptable_start = memremap(probed_rmp_base, probed_rmp_size, MEMREMAP_WB);
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if (!rmptable_start) {
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pr_err("Failed to map RMP table\n");
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return 1;
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}
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/*
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* Check if SEV-SNP is already enabled, this can happen in case of
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* kexec boot.
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*/
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rdmsrl(MSR_AMD64_SYSCFG, val);
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if (val & MSR_AMD64_SYSCFG_SNP_EN)
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goto skip_enable;
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memset(rmptable_start, 0, probed_rmp_size);
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/* Flush the caches to ensure that data is written before SNP is enabled. */
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wbinvd_on_all_cpus();
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/* MtrrFixDramModEn must be enabled on all the CPUs prior to enabling SNP. */
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on_each_cpu(mfd_enable, NULL, 1);
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on_each_cpu(snp_enable, NULL, 1);
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skip_enable:
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rmptable_start += RMPTABLE_CPU_BOOKKEEPING_SZ;
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rmptable_size = probed_rmp_size - RMPTABLE_CPU_BOOKKEEPING_SZ;
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rmptable = (struct rmpentry *)rmptable_start;
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rmptable_max_pfn = rmptable_size / sizeof(struct rmpentry) - 1;
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cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/rmptable_init:online", __snp_enable, NULL);
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return 0;
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nosnp:
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setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
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return -ENOSYS;
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}
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/*
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* This must be called after the IOMMU has been initialized.
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*/
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device_initcall(snp_rmptable_init);
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