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rt2x00: Disable synchronization during initialization
As soon as init_registers() was called, the rt2400/rt2500 would start raising beacondone interrupts. Since this is highly premature since no beacons were provided yet, we should initialize the synchronization register to 0. This will make all drivers initialize it to 0 regardless if they are raising beacondone interrupts or not, since it only makes sense to have it completely disabled. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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5 changed files with 47 additions and 0 deletions
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@ -731,6 +731,17 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
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(rt2x00dev->rx->data_size / 128));
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rt2x00pci_register_write(rt2x00dev, CSR9, reg);
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rt2x00pci_register_read(rt2x00dev, CSR14, ®);
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rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
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rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
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rt2x00_set_field32(®, CSR14_TBCN, 0);
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rt2x00_set_field32(®, CSR14_TCFP, 0);
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rt2x00_set_field32(®, CSR14_TATIMW, 0);
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rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
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rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
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rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
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rt2x00pci_register_write(rt2x00dev, CSR14, reg);
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rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
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rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
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@ -824,6 +824,17 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
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rt2x00pci_register_write(rt2x00dev, CSR11, reg);
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rt2x00pci_register_read(rt2x00dev, CSR14, ®);
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rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
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rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
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rt2x00_set_field32(®, CSR14_TBCN, 0);
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rt2x00_set_field32(®, CSR14_TCFP, 0);
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rt2x00_set_field32(®, CSR14_TATIMW, 0);
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rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
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rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
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rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
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rt2x00pci_register_write(rt2x00dev, CSR14, reg);
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rt2x00pci_register_write(rt2x00dev, CNT3, 0);
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rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
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@ -801,6 +801,13 @@ static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field16(®, TXRX_CSR8_BBP_ID1_VALID, 0);
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rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
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rt2500usb_register_read(rt2x00dev, TXRX_CSR19, ®);
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rt2x00_set_field16(®, TXRX_CSR19_TSF_COUNT, 0);
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rt2x00_set_field16(®, TXRX_CSR19_TSF_SYNC, 0);
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rt2x00_set_field16(®, TXRX_CSR19_TBCN, 0);
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rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 0);
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rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
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rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
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rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
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@ -1201,6 +1201,15 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
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rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
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rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
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rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
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rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
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rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
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rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
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rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
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@ -1006,6 +1006,15 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
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rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
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rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
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rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
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rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
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rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
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rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
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rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
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