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net: dsa: mv88e6xxx: prefix Global 2 remaining macros
Prefix and document the remaining Global 2 registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot
David S. Miller
parent
3b19df73ba
commit
1d90016d09
2 changed files with 57 additions and 35 deletions
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@ -1,6 +1,5 @@
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/*
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* Marvell 88E6xxx Switch Global 2 Registers support (device address
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* 0x1C)
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* Marvell 88E6xxx Switch Global 2 Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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@ -23,22 +22,22 @@
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static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val);
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return mv88e6xxx_read(chip, MV88E6XXX_G2, reg, val);
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}
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static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val);
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return mv88e6xxx_write(chip, MV88E6XXX_G2, reg, val);
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}
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static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
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{
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return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update);
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return mv88e6xxx_update(chip, MV88E6XXX_G2, reg, update);
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}
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static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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{
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return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);
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return mv88e6xxx_wait(chip, MV88E6XXX_G2, reg, mask);
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}
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/* Offset 0x02: Management Enable 2x */
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@ -258,7 +257,7 @@ static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
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{
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u16 val = (pointer << 8) | (data & 0x7);
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return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val);
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return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val);
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}
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static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
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@ -864,7 +863,7 @@ static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
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int err;
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chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
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GLOBAL2_INT_SOURCE_WATCHDOG);
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MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
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if (chip->watchdog_irq < 0)
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return chip->watchdog_irq;
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@ -891,16 +890,16 @@ static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
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u16 val;
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int err;
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err = mv88e6xxx_g2_read(chip, GLOBAL2_MISC, &val);
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err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
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if (err)
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return err;
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if (port_5_bit)
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val |= GLOBAL2_MISC_5_BIT_PORT;
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val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
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else
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val &= ~GLOBAL2_MISC_5_BIT_PORT;
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val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
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return mv88e6xxx_g2_write(chip, GLOBAL2_MISC, val);
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return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
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}
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int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
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@ -934,7 +933,7 @@ static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
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u16 reg;
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mutex_lock(&chip->reg_lock);
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err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, ®);
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err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SOURCE, ®);
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mutex_unlock(&chip->reg_lock);
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if (err)
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goto out;
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@ -961,7 +960,7 @@ static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
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{
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struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
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mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked);
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mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, ~chip->g2_irq.masked);
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mutex_unlock(&chip->reg_lock);
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}
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@ -1,5 +1,5 @@
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/*
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* Marvell 88E6xxx Switch Global 2 Registers support (device address 0x1C)
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* Marvell 88E6xxx Switch Global 2 Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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@ -17,11 +17,14 @@
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#include "chip.h"
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#define ADDR_GLOBAL2 0x1c
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#define MV88E6XXX_G2 0x1c
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#define GLOBAL2_INT_SOURCE 0x00
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#define GLOBAL2_INT_SOURCE_WATCHDOG 15
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#define GLOBAL2_INT_MASK 0x01
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/* Offset 0x00: Interrupt Source Register */
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#define MV88E6XXX_G2_INT_SOURCE 0x00
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#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
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/* Offset 0x01: Interrupt Mask Register */
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#define MV88E6XXX_G2_INT_MASK 0x01
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/* Offset 0x02: MGMT Enable Register 2x */
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#define MV88E6XXX_G2_MGMT_EN_2X 0x02
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@ -29,7 +32,8 @@
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/* Offset 0x03: MGMT Enable Register 0x */
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#define MV88E6XXX_G2_MGMT_EN_0X 0x03
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#define GLOBAL2_FLOW_CONTROL 0x04
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/* Offset 0x04: Flow Control Delay Register */
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#define MV88E6XXX_G2_FLOW_CTL 0x04
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/* Offset 0x05: Switch Management Register */
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#define MV88E6XXX_G2_SWITCH_MGMT 0x05
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@ -98,12 +102,18 @@
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#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
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#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
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#define GLOBAL2_ATU_STATS 0x0e
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#define GLOBAL2_PRIO_OVERRIDE 0x0f
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#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
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#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
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#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
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#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
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/* Offset 0x0E: ATU Stats Register */
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#define MV88E6XXX_G2_ATU_STATS 0x0e
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/* Offset 0x0F: Priority Override Table */
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#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
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#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
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#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
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#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
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#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080
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#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
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#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008
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#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
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/* Offset 0x14: EEPROM Command */
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#define MV88E6XXX_G2_EEPROM_CMD 0x14
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@ -125,8 +135,11 @@
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#define MV88E6390_G2_EEPROM_ADDR 0x15
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#define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
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#define GLOBAL2_PTP_AVB_OP 0x16
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#define GLOBAL2_PTP_AVB_DATA 0x17
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/* Offset 0x16: AVB Command Register */
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#define MV88E6352_G2_AVB_CMD 0x16
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/* Offset 0x17: AVB Data Register */
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#define MV88E6352_G2_AVB_DATA 0x17
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/* Offset 0x18: SMI PHY Command Register */
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#define MV88E6XXX_G2_SMI_PHY_CMD 0x18
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@ -152,10 +165,11 @@
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/* Offset 0x19: SMI PHY Data Register */
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#define MV88E6XXX_G2_SMI_PHY_DATA 0x19
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#define GLOBAL2_SCRATCH_MISC 0x1a
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#define GLOBAL2_SCRATCH_BUSY BIT(15)
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#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
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#define GLOBAL2_SCRATCH_VALUE_MASK 0xff
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/* Offset 0x1A: Scratch and Misc. Register */
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#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
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#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
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#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
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#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
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/* Offset 0x1B: Watch Dog Control Register */
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#define MV88E6352_G2_WDOG_CTL 0x1b
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@ -183,9 +197,18 @@
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#define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002
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#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
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#define GLOBAL2_QOS_WEIGHT 0x1c
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#define GLOBAL2_MISC 0x1d
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#define GLOBAL2_MISC_5_BIT_PORT BIT(14)
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/* Offset 0x1C: QoS Weights Register */
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#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
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#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
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#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
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#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
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#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
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/* Offset 0x1D: Misc Register */
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#define MV88E6XXX_G2_MISC 0x1d
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#define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
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#define MV88E6352_G2_NOEGR_POLICY 0x2000
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#define MV88E6390_G2_LAG_ID_4 0x2000
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#ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
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