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spi: Merge up fix

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One small fix that didn't seem worth sending before the merge window.
This commit is contained in:
Mark Brown 2023-10-30 13:20:58 +00:00
parent 75223bbea8 c3aa5cb264
commit 1b2e883e1a
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
9 changed files with 37 additions and 10 deletions
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7
Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml
View file

@ -22,6 +22,13 @@ properties:
- const: fsl,imx35-cspi
- const: fsl,imx51-ecspi
- const: fsl,imx53-ecspi
- items:
- enum:
- fsl,imx25-cspi
- fsl,imx50-cspi
- fsl,imx51-cspi
- fsl,imx53-cspi
- const: fsl,imx35-cspi
- items:
- const: fsl,imx8mp-ecspi
- const: fsl,imx6ul-ecspi

1
drivers/spi/spi-cs42l43.c
View file

@ -256,7 +256,6 @@ static int cs42l43_spi_probe(struct platform_device *pdev)
ret = devm_spi_register_controller(priv->dev, priv->ctlr);
if (ret) {
pm_runtime_disable(priv->dev);
dev_err(priv->dev, "Failed to register SPI controller: %d\n", ret);
}

2
drivers/spi/spi-gxp.c
View file

@ -194,7 +194,7 @@ static ssize_t gxp_spi_write(struct gxp_spi_chip *chip, const struct spi_mem_op
return ret;
}
return write_len;
return 0;
}
static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)

2
drivers/spi/spi-imx.c
View file

@ -662,7 +662,7 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
if (spi_imx->count >= 512)
ctrl |= 0xFFF << MX51_ECSPI_CTRL_BL_OFFSET;
else
ctrl |= (spi_imx->count*8 - 1)
ctrl |= (spi_imx->count * spi_imx->bits_per_word - 1)
<< MX51_ECSPI_CTRL_BL_OFFSET;
}

1
drivers/spi/spi-intel-pci.c
View file

@ -72,6 +72,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x51a4), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x54a4), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x5794), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x7a24), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x7e23), (unsigned long)&cnl_info },

5
drivers/spi/spi-npcm-fiu.c
View file

@ -353,8 +353,9 @@ static int npcm_fiu_uma_read(struct spi_mem *mem,
uma_cfg |= ilog2(op->cmd.buswidth);
uma_cfg |= ilog2(op->addr.buswidth)
<< NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
uma_cfg |= ilog2(op->dummy.buswidth)
<< NPCM_FIU_UMA_CFG_DBPCK_SHIFT;
if (op->dummy.nbytes)
uma_cfg |= ilog2(op->dummy.buswidth)
<< NPCM_FIU_UMA_CFG_DBPCK_SHIFT;
uma_cfg |= ilog2(op->data.buswidth)
<< NPCM_FIU_UMA_CFG_RDBPCK_SHIFT;
uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT;

9
drivers/spi/spi-nxp-fspi.c
View file

@ -759,7 +759,7 @@ static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
f->memmap_len = len > NXP_FSPI_MIN_IOMAP ?
len : NXP_FSPI_MIN_IOMAP;
f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start,
f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start,
f->memmap_len);
if (!f->ahb_addr) {
@ -1084,6 +1084,13 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
base + FSPI_AHBCR);
/* Reset the FLSHxCR1 registers. */
reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3);
fspi_writel(f, reg, base + FSPI_FLSHA1CR1);
fspi_writel(f, reg, base + FSPI_FLSHA2CR1);
fspi_writel(f, reg, base + FSPI_FLSHB1CR1);
fspi_writel(f, reg, base + FSPI_FLSHB2CR1);
/* AHB Read - Set lut sequence ID for all CS. */
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);

8
drivers/spi/spi-stm32.c
View file

@ -278,6 +278,7 @@ struct stm32_spi_cfg {
* @fifo_size: size of the embedded fifo in bytes
* @cur_midi: master inter-data idleness in ns
* @cur_speed: speed configured in Hz
* @cur_half_period: time of a half bit in us
* @cur_bpw: number of bits in a single SPI data frame
* @cur_fthlv: fifo threshold level (data frames in a single data packet)
* @cur_comm: SPI communication mode
@ -305,6 +306,7 @@ struct stm32_spi {
unsigned int cur_midi;
unsigned int cur_speed;
unsigned int cur_half_period;
unsigned int cur_bpw;
unsigned int cur_fthlv;
unsigned int cur_comm;
@ -469,6 +471,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
return mbrdiv - 1;
}
@ -710,6 +714,10 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
return;
}
/* Add a delay to make sure that transmission is ended. */
if (spi->cur_half_period)
udelay(spi->cur_half_period);
if (spi->cur_usedma && spi->dma_tx)
dmaengine_terminate_async(spi->dma_tx);
if (spi->cur_usedma && spi->dma_rx)

12
drivers/spi/spi-zynqmp-gqspi.c
View file

@ -1340,9 +1340,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
return 0;
clk_dis_all:
pm_runtime_put_sync(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
clk_disable_unprepare(xqspi->refclk);
clk_dis_pclk:
clk_disable_unprepare(xqspi->pclk);
@ -1366,11 +1366,15 @@ static void zynqmp_qspi_remove(struct platform_device *pdev)
{
struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
pm_runtime_get_sync(&pdev->dev);
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
pm_runtime_disable(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
clk_disable_unprepare(xqspi->refclk);
clk_disable_unprepare(xqspi->pclk);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);