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irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel}
This effectively converts the __raw_ accessors to the non-__raw_ equivalents. To handle BE, we pass IRQ_GC_BE_IO, similar to what was done in irq-bcm7120-l2.c. Since irq_reg_writel now takes an irq_chip_generic argument, writel must be used for the initial hardware reset in the probe function. But that operation never needs endian swapping, so it's probably not a big deal. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-15-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
parent
c17261fac3
commit
1abbdbac36
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@ -18,6 +18,7 @@
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/kconfig.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of.h>
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@ -53,13 +54,14 @@ struct brcmstb_l2_intc_data {
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static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
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static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
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{
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{
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struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
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struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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u32 status;
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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status = __raw_readl(b->base + CPU_STATUS) &
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status = irq_reg_readl(gc, CPU_STATUS) &
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~(__raw_readl(b->base + CPU_MASK_STATUS));
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~(irq_reg_readl(gc, CPU_MASK_STATUS));
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if (status == 0) {
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if (status == 0) {
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raw_spin_lock(&desc->lock);
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raw_spin_lock(&desc->lock);
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@ -71,7 +73,7 @@ static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
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do {
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do {
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irq = ffs(status) - 1;
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irq = ffs(status) - 1;
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/* ack at our level */
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/* ack at our level */
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__raw_writel(1 << irq, b->base + CPU_CLEAR);
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irq_reg_writel(gc, 1 << irq, CPU_CLEAR);
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status &= ~(1 << irq);
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status &= ~(1 << irq);
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generic_handle_irq(irq_find_mapping(b->domain, irq));
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generic_handle_irq(irq_find_mapping(b->domain, irq));
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} while (status);
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} while (status);
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@ -86,12 +88,12 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
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irq_gc_lock(gc);
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irq_gc_lock(gc);
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/* Save the current mask */
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/* Save the current mask */
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b->saved_mask = __raw_readl(b->base + CPU_MASK_STATUS);
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b->saved_mask = irq_reg_readl(gc, CPU_MASK_STATUS);
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if (b->can_wake) {
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if (b->can_wake) {
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/* Program the wakeup mask */
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/* Program the wakeup mask */
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__raw_writel(~gc->wake_active, b->base + CPU_MASK_SET);
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irq_reg_writel(gc, ~gc->wake_active, CPU_MASK_SET);
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__raw_writel(gc->wake_active, b->base + CPU_MASK_CLEAR);
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irq_reg_writel(gc, gc->wake_active, CPU_MASK_CLEAR);
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}
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}
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irq_gc_unlock(gc);
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irq_gc_unlock(gc);
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}
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}
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@ -103,11 +105,11 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
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irq_gc_lock(gc);
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irq_gc_lock(gc);
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/* Clear unmasked non-wakeup interrupts */
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/* Clear unmasked non-wakeup interrupts */
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__raw_writel(~b->saved_mask & ~gc->wake_active, b->base + CPU_CLEAR);
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irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, CPU_CLEAR);
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/* Restore the saved mask */
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/* Restore the saved mask */
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__raw_writel(b->saved_mask, b->base + CPU_MASK_SET);
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irq_reg_writel(gc, b->saved_mask, CPU_MASK_SET);
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__raw_writel(~b->saved_mask, b->base + CPU_MASK_CLEAR);
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irq_reg_writel(gc, ~b->saved_mask, CPU_MASK_CLEAR);
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irq_gc_unlock(gc);
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irq_gc_unlock(gc);
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}
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}
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@ -119,6 +121,7 @@ int __init brcmstb_l2_intc_of_init(struct device_node *np,
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struct irq_chip_generic *gc;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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struct irq_chip_type *ct;
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int ret;
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int ret;
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unsigned int flags;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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if (!data)
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@ -132,8 +135,8 @@ int __init brcmstb_l2_intc_of_init(struct device_node *np,
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}
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}
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/* Disable all interrupts by default */
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/* Disable all interrupts by default */
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__raw_writel(0xffffffff, data->base + CPU_MASK_SET);
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writel(0xffffffff, data->base + CPU_MASK_SET);
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__raw_writel(0xffffffff, data->base + CPU_CLEAR);
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writel(0xffffffff, data->base + CPU_CLEAR);
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data->parent_irq = irq_of_parse_and_map(np, 0);
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data->parent_irq = irq_of_parse_and_map(np, 0);
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if (data->parent_irq < 0) {
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if (data->parent_irq < 0) {
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@ -149,9 +152,16 @@ int __init brcmstb_l2_intc_of_init(struct device_node *np,
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goto out_unmap;
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goto out_unmap;
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}
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}
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/* MIPS chips strapped for BE will automagically configure the
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* peripheral registers for CPU-native byte order.
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*/
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flags = 0;
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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flags |= IRQ_GC_BE_IO;
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/* Allocate a single Generic IRQ chip for this node */
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/* Allocate a single Generic IRQ chip for this node */
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
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np->full_name, handle_edge_irq, clr, 0, 0);
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np->full_name, handle_edge_irq, clr, 0, flags);
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if (ret) {
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if (ret) {
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pr_err("failed to allocate generic irq chip\n");
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pr_err("failed to allocate generic irq chip\n");
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goto out_free_domain;
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goto out_free_domain;
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