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https://github.com/torvalds/linux
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ARM: dts: ipq4019: Add a few peripheral nodes
Now with the driver updates for some peripherals being there, add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available peripheral support. Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Sricharan R
Andy Gross
parent
c696a02019
commit
1875194032
2 changed files with 146 additions and 12 deletions
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@ -69,7 +69,7 @@ blsp_dma: dma@7884000 {
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status = "ok";
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};
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spi_0: spi@78b5000 {
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spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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@ -40,8 +40,10 @@ tz@87e80000 {
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};
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aliases {
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spi0 = &spi_0;
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i2c0 = &i2c_0;
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spi0 = &blsp1_spi1;
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spi1 = &blsp1_spi2;
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i2c0 = &blsp1_i2c3;
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i2c1 = &blsp1_i2c4;
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};
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cpus {
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@ -120,6 +122,12 @@ xo: xo {
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq4019";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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@ -165,13 +173,13 @@ tlmm: pinctrl@1000000 {
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@ -179,7 +187,7 @@ blsp_dma: dma@7884000 {
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status = "disabled";
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};
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spi_0: spi@78b5000 {
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blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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@ -188,10 +196,26 @@ spi_0: spi@78b5000 {
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 5>, <&blsp_dma 4>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c_0: i2c@78b7000 {
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blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 7>, <&blsp_dma 6>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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@ -200,14 +224,29 @@ i2c_0: i2c@78b7000 {
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 9>, <&blsp_dma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b8000 0x600>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 11>, <&blsp_dma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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cryptobam: dma@8e04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x08e04000 0x20000>;
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interrupts = <GIC_SPI 207 0>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@ -275,7 +314,7 @@ saw3: regulator@b0b9000 {
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <0 107 0>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@ -287,7 +326,7 @@ blsp1_uart1: serial@78af000 {
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serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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interrupts = <0 108 0>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@ -309,6 +348,101 @@ restart@4ab000 {
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reg = <0x4ab000 0x4>;
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};
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pcie0: pci@40000000 {
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compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
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reg = <0x40000000 0xf1d
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0x40000f20 0xa8
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0x80000 0x2000
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0x40100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
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0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_AHB_CLK>,
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<&gcc GCC_PCIE_AXI_M_CLK>,
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<&gcc GCC_PCIE_AXI_S_CLK>;
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clock-names = "aux",
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"master_bus",
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"slave_bus";
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resets = <&gcc PCIE_AXI_M_ARES>,
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<&gcc PCIE_AXI_S_ARES>,
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<&gcc PCIE_PIPE_ARES>,
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<&gcc PCIE_AXI_M_VMIDMT_ARES>,
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<&gcc PCIE_AXI_S_XPU_ARES>,
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<&gcc PCIE_PARF_XPU_ARES>,
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<&gcc PCIE_PHY_ARES>,
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<&gcc PCIE_AXI_M_STICKY_ARES>,
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<&gcc PCIE_PIPE_STICKY_ARES>,
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<&gcc PCIE_PWR_ARES>,
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<&gcc PCIE_AHB_ARES>,
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<&gcc PCIE_PHY_AHB_ARES>;
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reset-names = "axi_m",
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"axi_s",
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"pipe",
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"axi_m_vmid",
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"axi_s_xpu",
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"parf",
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"phy",
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"axi_m_sticky",
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"pipe_sticky",
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"pwr",
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"ahb",
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"phy_ahb";
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status = "disabled";
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};
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qpic_bam: dma@7984000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7984000 0x1a000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QPIC_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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nand: qpic-nand@79b0000 {
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compatible = "qcom,ipq4019-nand";
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reg = <0x79b0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "core", "aon";
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dmas = <&qpic_bam 0>,
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<&qpic_bam 1>,
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<&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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status = "disabled";
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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};
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};
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wifi0: wifi@a000000 {
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compatible = "qcom,ipq4019-wifi";
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reg = <0xa000000 0x200000>;
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@ -342,7 +476,7 @@ wifi0: wifi@a000000 {
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<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 168 IRQ_TYPE_NONE>;
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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@ -384,7 +518,7 @@ wifi1: wifi@a800000 {
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<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 169 IRQ_TYPE_NONE>;
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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