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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

Browse source 
Cross-merge networking fixes after downstream PR.

Conflicts:

include/linux/mlx5/driver.h
  617f5db1a6 ("RDMA/mlx5: Fix affinity assignment")
  dc13180824 ("net/mlx5: Enable devlink port for embedded cpu VF vports")
https://lore.kernel.org/all/20230613125939.595e50b8@canb.auug.org.au/

tools/testing/selftests/net/mptcp/mptcp_join.sh
  47867f0a7e ("selftests: mptcp: join: skip check if MIB counter not supported")
  425ba80312 ("selftests: mptcp: join: support RM_ADDR for used endpoints or not")
  45b1a1227a ("mptcp: introduces more address related mibs")
  0639fa230a ("selftests: mptcp: add explicit check for new mibs")
https://lore.kernel.org/netdev/20230609-upstream-net-20230610-mptcp-selftests-support-old-kernels-part-3-v1-0-2896fe2ee8a3@tessares.net/

No adjacent changes.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2023-06-15 22:18:58 -07:00
parent 97c5209b3d 40f71e7cd3
commit 173780ff18
366 changed files with 3266 additions and 1621 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
.mailmap
View file

@ -233,6 +233,7 @@ Jisheng Zhang <jszhang@kernel.org> <Jisheng.Zhang@synaptics.com>
Johan Hovold <johan@kernel.org> <jhovold@gmail.com>
Johan Hovold <johan@kernel.org> <johan@hovoldconsulting.com>
John Crispin <john@phrozen.org> <blogic@openwrt.org>
John Keeping <john@keeping.me.uk> <john@metanate.com>
John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
John Stultz <johnstul@us.ibm.com>
<jon.toppins+linux@gmail.com> <jtoppins@cumulusnetworks.com>

22
Documentation/admin-guide/cgroup-v2.rst
View file

@ -1213,23 +1213,25 @@ PAGE_SIZE multiple when read back.
A read-write single value file which exists on non-root
cgroups. The default is "max".
Memory usage throttle limit. This is the main mechanism to
control memory usage of a cgroup. If a cgroup's usage goes
Memory usage throttle limit. If a cgroup's usage goes
over the high boundary, the processes of the cgroup are
throttled and put under heavy reclaim pressure.
Going over the high limit never invokes the OOM killer and
under extreme conditions the limit may be breached.
under extreme conditions the limit may be breached. The high
limit should be used in scenarios where an external process
monitors the limited cgroup to alleviate heavy reclaim
pressure.
memory.max
A read-write single value file which exists on non-root
cgroups. The default is "max".
Memory usage hard limit. This is the final protection
mechanism. If a cgroup's memory usage reaches this limit and
can't be reduced, the OOM killer is invoked in the cgroup.
Under certain circumstances, the usage may go over the limit
temporarily.
Memory usage hard limit. This is the main mechanism to limit
memory usage of a cgroup. If a cgroup's memory usage reaches
this limit and can't be reduced, the OOM killer is invoked in
the cgroup. Under certain circumstances, the usage may go
over the limit temporarily.
In default configuration regular 0-order allocations always
succeed unless OOM killer chooses current task as a victim.
@ -1238,10 +1240,6 @@ PAGE_SIZE multiple when read back.
Caller could retry them differently, return into userspace
as -ENOMEM or silently ignore in cases like disk readahead.
This is the ultimate protection mechanism. As long as the
high limit is used and monitored properly, this limit's
utility is limited to providing the final safety net.
memory.reclaim
A write-only nested-keyed file which exists for all cgroups.

2
Documentation/devicetree/bindings/ata/ahci-common.yaml
View file

@ -8,7 +8,7 @@ title: Common Properties for Serial ATA AHCI controllers
maintainers:
- Hans de Goede <hdegoede@redhat.com>
- Damien Le Moal <damien.lemoal@opensource.wdc.com>
- Damien Le Moal <dlemoal@kernel.org>
description:
This document defines device tree properties for a common AHCI SATA

1
Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View file

@ -129,6 +129,7 @@ allOf:
- qcom,sm8250-llcc
- qcom,sm8350-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
then:
properties:
reg:

2
Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 Clock
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
- Damien Le Moal <dlemoal@kernel.org>
description: |
Canaan Kendryte K210 SoC clocks driver bindings. The clock

2
Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml
View file

@ -44,7 +44,7 @@ required:
- clock-names
- clocks
additionalProperties: true
unevaluatedProperties: false
examples:
- |

2
Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 System Controller
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
- Damien Le Moal <dlemoal@kernel.org>
description:
Canaan Inc. Kendryte K210 SoC system controller which provides a

4
Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
View file

@ -11,7 +11,7 @@ maintainers:
- Alistair Francis <alistair@alistair23.me>
description:
RTL8723CS/RTL8723CS/RTL8821CS/RTL8822CS is a WiFi + BT chip. WiFi part
RTL8723BS/RTL8723CS/RTL8821CS/RTL8822CS is a WiFi + BT chip. WiFi part
is connected over SDIO, while BT is connected over serial. It speaks
H5 protocol with few extra commands to upload firmware and change
module speed.
@ -27,7 +27,7 @@ properties:
- items:
- enum:
- realtek,rtl8821cs-bt
- const: realtek,rtl8822cs-bt
- const: realtek,rtl8723bs-bt
device-wake-gpios:
maxItems: 1

2
Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 FPIOA
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
- Damien Le Moal <dlemoal@kernel.org>
description:
The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)

5
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
View file

@ -144,8 +144,9 @@ $defs:
enum: [0, 1, 2, 3, 4, 5, 6, 7]
qcom,paired:
- description:
Indicates that the pin should be operating in paired mode.
type: boolean
description:
Indicates that the pin should be operating in paired mode.
required:
- pins

1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
View file

@ -29,6 +29,7 @@ properties:
- qcom,qcm2290-rpmpd
- qcom,qcs404-rpmpd
- qcom,qdu1000-rpmhpd
- qcom,sa8155p-rpmhpd
- qcom,sa8540p-rpmhpd
- qcom,sa8775p-rpmhpd
- qcom,sdm660-rpmpd

2
Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 Reset Controller
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
- Damien Le Moal <dlemoal@kernel.org>
description: |
Canaan Kendryte K210 reset controller driver which supports the SoC

2
Documentation/devicetree/bindings/riscv/canaan.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan SoC-based boards
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
- Damien Le Moal <dlemoal@kernel.org>
description:
Canaan Kendryte K210 SoC-based boards

2
Documentation/devicetree/usage-model.rst
View file

@ -415,6 +415,6 @@ When using the DT, this creates problems for of_platform_populate()
because it must decide whether to register each node as either a
platform_device or an amba_device. This unfortunately complicates the
device creation model a little bit, but the solution turns out not to
be too invasive. If a node is compatible with "arm,amba-primecell", then
be too invasive. If a node is compatible with "arm,primecell", then
of_platform_populate() will register it as an amba_device instead of a
platform_device.

2
Documentation/translations/zh_CN/devicetree/usage-model.rst
View file

@ -325,6 +325,6 @@ Primecell设备。然而，棘手的一点是，AMBA总线上的所有设备并
当使用DT时，这给of_platform_populate()带来了问题，因为它必须决定是否将
每个节点注册为platform_device或amba_device。不幸的是，这使设备创建模型
变得有点复杂，但解决方案原来并不是太具有侵略性。如果一个节点与“arm,amba-primecell”
变得有点复杂，但解决方案原来并不是太具有侵略性。如果一个节点与“arm,primecell”
兼容，那么of_platform_populate()将把它注册为amba_device而不是
platform_device。

15
MAINTAINERS
View file

@ -8798,6 +8798,7 @@ F: include/linux/gpio/regmap.h
GPIO SUBSYSTEM
M: Linus Walleij <linus.walleij@linaro.org>
M: Bartosz Golaszewski <brgl@bgdev.pl>
R: Andy Shevchenko <andy@kernel.org>
L: linux-gpio@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
@ -9694,8 +9695,9 @@ F: include/uapi/linux/i2c-*.h
F: include/uapi/linux/i2c.h
I2C SUBSYSTEM HOST DRIVERS
M: Andi Shyti <andi.shyti@kernel.org>
L: linux-i2c@vger.kernel.org
S: Odd Fixes
S: Maintained
W: https://i2c.wiki.kernel.org/
Q: https://patchwork.ozlabs.org/project/linux-i2c/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
@ -18060,6 +18062,14 @@ S: Maintained
F: Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml
F: drivers/usb/gadget/udc/renesas_usbf.c
RENESAS RZ/V2M I2C DRIVER
M: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
L: linux-i2c@vger.kernel.org
L: linux-renesas-soc@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml
F: drivers/i2c/busses/i2c-rzv2m.c
RENESAS USB PHY DRIVER
M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
L: linux-renesas-soc@vger.kernel.org
@ -19144,6 +19154,9 @@ SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
M: Karsten Graul <kgraul@linux.ibm.com>
M: Wenjia Zhang <wenjia@linux.ibm.com>
M: Jan Karcher <jaka@linux.ibm.com>
R: D. Wythe <alibuda@linux.alibaba.com>
R: Tony Lu <tonylu@linux.alibaba.com>
R: Wen Gu <guwen@linux.alibaba.com>
L: linux-s390@vger.kernel.org
S: Supported
F: net/smc/

2
Makefile
View file

@ -2,7 +2,7 @@
VERSION = 6
PATCHLEVEL = 4
SUBLEVEL = 0
EXTRAVERSION = -rc5
EXTRAVERSION = -rc6
NAME = Hurr durr I'ma ninja sloth
# *DOCUMENTATION*

2
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
View file

@ -527,7 +527,7 @@ touchscreen@1 {
interrupt-parent = <&gpio1>;
interrupts = <31 0>;
pendown-gpio = <&gpio1 31 0>;
pendown-gpio = <&gpio1 31 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <0x0>;

2
arch/arm/boot/dts/at91-sama7g5ek.dts
View file

@ -792,7 +792,7 @@ &sdmmc2 {
};
&shdwc {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
status = "okay";
input@0 {

2
arch/arm/boot/dts/at91sam9261ek.dts
View file

@ -156,7 +156,7 @@ tsc2046@2 {
compatible = "ti,ads7843";
interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
spi-max-frequency = <3000000>;
pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&pioC 2 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <150>;
ti,x-max = /bits/ 16 <3830>;

2
arch/arm/boot/dts/imx7d-pico-hobbit.dts
View file

@ -64,7 +64,7 @@ ads7846@0 {
interrupt-parent = <&gpio2>;
interrupts = <7 0>;
spi-max-frequency = <1000000>;
pendown-gpio = <&gpio2 7 0>;
pendown-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
vcc-supply = <&reg_3p3v>;
ti,x-min = /bits/ 16 <0>;
ti,x-max = /bits/ 16 <4095>;

2
arch/arm/boot/dts/imx7d-sdb.dts
View file

@ -205,7 +205,7 @@ tsc2046@0 {
pinctrl-0 = <&pinctrl_tsc2046_pendown>;
interrupt-parent = <&gpio2>;
interrupts = <29 0>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
touchscreen-max-pressure = <255>;
wakeup-source;
};

2
arch/arm/boot/dts/omap3-cm-t3x.dtsi
View file

@ -227,7 +227,7 @@ ads7846@0 {
interrupt-parent = <&gpio2>;
interrupts = <25 0>; /* gpio_57 */
pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <0x0>;
ti,x-max = /bits/ 16 <0x0fff>;

2
arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi
View file

@ -54,7 +54,7 @@ ads7846@0 {
interrupt-parent = <&gpio1>;
interrupts = <27 0>; /* gpio_27 */
pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <0x0>;
ti,x-max = /bits/ 16 <0x0fff>;

2
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
View file

@ -311,7 +311,7 @@ tsc2046@0 {
interrupt-parent = <&gpio1>;
interrupts = <8 0>; /* boot6 / gpio_8 */
spi-max-frequency = <1000000>;
pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
vcc-supply = <&reg_vcc3>;
pinctrl-names = "default";
pinctrl-0 = <&tsc2048_pins>;

2
arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
View file

@ -149,7 +149,7 @@ ads7846@0 {
interrupt-parent = <&gpio4>;
interrupts = <18 0>; /* gpio_114 */
pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio4 18 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <0x0>;
ti,x-max = /bits/ 16 <0x0fff>;

2
arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
View file

@ -160,7 +160,7 @@ ads7846@0 {
interrupt-parent = <&gpio4>;
interrupts = <18 0>; /* gpio_114 */
pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio4 18 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <0x0>;
ti,x-max = /bits/ 16 <0x0fff>;

2
arch/arm/boot/dts/omap3-pandora-common.dtsi
View file

@ -651,7 +651,7 @@ tsc2046@0 {
pinctrl-0 = <&penirq_pins>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */
pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio3 30 GPIO_ACTIVE_LOW>;
vcc-supply = <&vaux4>;
ti,x-min = /bits/ 16 <0>;

2
arch/arm/boot/dts/omap5-cm-t54.dts
View file

@ -354,7 +354,7 @@ ads7846@0 {
interrupt-parent = <&gpio1>;
interrupts = <15 0>; /* gpio1_wk15 */
pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
pendown-gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <0x0>;

2
arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts
View file

@ -268,7 +268,6 @@ bluetooth_default_state: bluetooth-default-state {
function = "gpio";
drive-strength = <8>;
bias-disable;
input-enable;
};
wlan_hostwake_default_state: wlan-hostwake-default-state {
@ -276,7 +275,6 @@ wlan_hostwake_default_state: wlan-hostwake-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
wlan_regulator_default_state: wlan-regulator-default-state {

1
arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts
View file

@ -352,7 +352,6 @@ wlan_hostwake_default_state: wlan-hostwake-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
wlan_regulator_default_state: wlan-regulator-default-state {

3
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
View file

@ -307,7 +307,6 @@ bluetooth_default_state: bluetooth-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
touch_pins: touch-state {
@ -317,7 +316,6 @@ irq-pins {
drive-strength = <8>;
bias-pull-down;
input-enable;
};
reset-pins {
@ -335,7 +333,6 @@ wlan_hostwake_default_state: wlan-hostwake-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
wlan_regulator_default_state: wlan-regulator-default-state {

1
arch/arm/boot/dts/qcom-apq8064.dtsi
View file

@ -83,6 +83,7 @@ CPU3: cpu@3 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {

1
arch/arm/boot/dts/qcom-apq8084.dtsi
View file

@ -74,6 +74,7 @@ cpu@3 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
qcom,saw = <&saw_l2>;
};

1
arch/arm/boot/dts/qcom-ipq4019.dtsi
View file

@ -102,6 +102,7 @@ cpu@3 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
qcom,saw = <&saw_l2>;
};
};

1
arch/arm/boot/dts/qcom-ipq8064.dtsi
View file

@ -45,6 +45,7 @@ cpu1: cpu@1 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
View file

@ -49,7 +49,6 @@ gpioext1_pins: gpioext1-state {
gpioext1-pins {
pins = "gpio2";
function = "gpio";
input-enable;
bias-disable;
};
};

1
arch/arm/boot/dts/qcom-msm8660.dtsi
View file

@ -36,6 +36,7 @@ cpu@1 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm/boot/dts/qcom-msm8960.dtsi
View file

@ -42,6 +42,7 @@ cpu@1 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
View file

@ -592,7 +592,6 @@ mpu6515_pin: mpu6515-state {
pins = "gpio73";
function = "gpio";
bias-disable;
input-enable;
};
touch_pin: touch-state {
@ -602,7 +601,6 @@ int-pins {
drive-strength = <2>;
bias-disable;
input-enable;
};
reset-pins {

1
arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
View file

@ -433,7 +433,6 @@ ts_int_pin: touch-int-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
sdc1_on: sdc1-on-state {

1
arch/arm/boot/dts/qcom-msm8974.dtsi
View file

@ -80,6 +80,7 @@ CPU3: cpu@3 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
qcom,saw = <&saw_l2>;
};

1
arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts
View file

@ -461,7 +461,6 @@ int-pins {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
reset-pins {

4
arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
View file

@ -704,7 +704,6 @@ hostwake-pins {
pins = "gpio75";
function = "gpio";
drive-strength = <16>;
input-enable;
};
devwake-pins {
@ -760,14 +759,12 @@ cmd-data-pins {
i2c_touchkey_pins: i2c-touchkey-state {
pins = "gpio95", "gpio96";
function = "gpio";
input-enable;
bias-pull-up;
};
i2c_led_gpioex_pins: i2c-led-gpioex-state {
pins = "gpio120", "gpio121";
function = "gpio";
input-enable;
bias-pull-down;
};
@ -781,7 +778,6 @@ gpioex_pin: gpioex-state {
wifi_pin: wifi-state {
pins = "gpio92";
function = "gpio";
input-enable;
bias-pull-down;
};

1
arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
View file

@ -631,7 +631,6 @@ ts_int_pin: ts-int-pin-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
bt_host_wake_pin: bt-host-wake-state {

20
arch/arm/mach-at91/pm.c
View file

@ -334,16 +334,14 @@ static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
pdev = of_find_device_by_node(eth->np);
if (!pdev)
return false;
/* put_device(eth->dev) is called at the end of suspend. */
eth->dev = &pdev->dev;
}
/* No quirks if device isn't a wakeup source. */
if (!device_may_wakeup(eth->dev)) {
put_device(eth->dev);
if (!device_may_wakeup(eth->dev))
return false;
}
/* put_device(eth->dev) is called at the end of suspend. */
return true;
}
@ -439,14 +437,14 @@ static int at91_pm_config_quirks(bool suspend)
pr_err("AT91: PM: failed to enable %s clocks\n",
j == AT91_PM_G_ETH ? "geth" : "eth");
}
} else {
/*
* Release the reference to eth->dev taken in
* at91_pm_eth_quirk_is_valid().
*/
put_device(eth->dev);
eth->dev = NULL;
}
/*
* Release the reference to eth->dev taken in
* at91_pm_eth_quirk_is_valid().
*/
put_device(eth->dev);
eth->dev = NULL;
}
return ret;

2
arch/arm64/Kconfig
View file

@ -1516,7 +1516,7 @@ config XEN
# 16K | 27 | 14 | 13 | 11 |
# 64K | 29 | 16 | 13 | 13 |
config ARCH_FORCE_MAX_ORDER
int "Order of maximal physically contiguous allocations" if EXPERT && (ARM64_4K_PAGES || ARM64_16K_PAGES)
int
default "13" if ARM64_64K_PAGES
default "11" if ARM64_16K_PAGES
default "10"

8
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View file

@ -90,6 +90,8 @@ lpuart0: serial@5a060000 {
clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
<&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
};
@ -100,6 +102,8 @@ lpuart1: serial@5a070000 {
clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
<&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
@ -110,6 +114,8 @@ lpuart2: serial@5a080000 {
clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
<&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
@ -120,6 +126,8 @@ lpuart3: serial@5a090000 {
clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
<&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};

4
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
View file

@ -81,7 +81,7 @@ sound {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
@ -202,7 +202,7 @@ pinctrl_espi2: espi2grp {
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
>;
};

4
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View file

@ -82,8 +82,8 @@ &usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};

1
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View file

@ -73,6 +73,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

3
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file

@ -83,7 +83,8 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
cache-level = <2>;
cache-unified;
};
};

3
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file

@ -66,7 +66,8 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View file

@ -72,6 +72,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -180,6 +180,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {

2
arch/arm64/boot/dts/qcom/msm8953.dtsi
View file

@ -153,11 +153,13 @@ core3 {
L2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
L2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/qcom/msm8976.dtsi
View file

@ -193,11 +193,13 @@ big_cpu_sleep_1: cpu-sleep-1-1 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file

@ -52,6 +52,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -88,6 +89,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

10
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file

@ -53,8 +53,9 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -83,8 +84,9 @@ CPU2: cpu@100 {
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file

@ -146,6 +146,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -190,6 +191,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View file

@ -51,6 +51,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file

@ -95,6 +95,7 @@ CPU3: cpu@103 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {

10
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View file

@ -35,9 +35,13 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -54,6 +58,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -70,6 +76,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -86,6 +94,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

2
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View file

@ -7,7 +7,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/gpio/gpio.h>
#include "sm8150.dtsi"
#include "sa8155p.dtsi"
#include "pmm8155au_1.dtsi"
#include "pmm8155au_2.dtsi"

40
arch/arm64/boot/dts/qcom/sa8155p.dtsi Normal file
View file

@ -0,0 +1,40 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*
* SA8155P is an automotive variant of SM8150, with some minor changes.
* Most notably, the RPMhPD setup differs: MMCX and LCX/LMX rails are gone,
* though the cmd-db doesn't reflect that and access attemps result in a bite.
*/
#include "sm8150.dtsi"
&dispcc {
power-domains = <&rpmhpd SA8155P_CX>;
};
&mdss_dsi0 {
power-domains = <&rpmhpd SA8155P_CX>;
};
&mdss_dsi1 {
power-domains = <&rpmhpd SA8155P_CX>;
};
&mdss_mdp {
power-domains = <&rpmhpd SA8155P_CX>;
};
&remoteproc_slpi {
power-domains = <&rpmhpd SA8155P_CX>,
<&rpmhpd SA8155P_MX>;
};
&rpmhpd {
/*
* The bindings were crafted such that SA8155P PDs match their
* SM8150 counterparts to make it more maintainable and only
* necessitate adjusting entries that actually differ
*/
compatible = "qcom,sa8155p-rpmhpd";
};

20
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View file

@ -42,9 +42,13 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -58,6 +62,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -71,6 +77,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -84,6 +92,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -97,9 +107,13 @@ CPU4: cpu@10000 {
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
L3_1: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
@ -114,6 +128,8 @@ CPU5: cpu@10100 {
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
@ -127,6 +143,8 @@ CPU6: cpu@10200 {
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
@ -140,6 +158,8 @@ CPU7: cpu@10300 {
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};

8
arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
View file

@ -16,3 +16,11 @@ &cpu6_opp11 {
&cpu6_opp12 {
opp-peak-kBps = <8532000 23347200>;
};
&cpu6_opp13 {
opp-peak-kBps = <8532000 23347200>;
};
&cpu6_opp14 {
opp-peak-kBps = <8532000 23347200>;
};

9
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -92,10 +92,12 @@ &LITTLE_CPU_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -120,6 +122,7 @@ &LITTLE_CPU_SLEEP_1
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -144,6 +147,7 @@ &LITTLE_CPU_SLEEP_1
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -168,6 +172,7 @@ &LITTLE_CPU_SLEEP_1
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -192,6 +197,7 @@ &LITTLE_CPU_SLEEP_1
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -216,6 +222,7 @@ &LITTLE_CPU_SLEEP_1
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -240,6 +247,7 @@ &BIG_CPU_SLEEP_1
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -264,6 +272,7 @@ &BIG_CPU_SLEEP_1
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

2
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View file

@ -480,7 +480,6 @@ &swr0 {
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
#sound-dai-cells = <1>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
@ -491,7 +490,6 @@ &swr1 {
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
#sound-dai-cells = <1>;
qcom,tx-port-mapping = <1 2 3 4>;
};
};

2
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View file

@ -414,7 +414,6 @@ &swr0 {
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
#sound-dai-cells = <1>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
@ -423,7 +422,6 @@ &swr1 {
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
#sound-dai-cells = <1>;
qcom,tx-port-mapping = <1 2 3 4>;
};
};

9
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file

@ -182,10 +182,12 @@ &LITTLE_CPU_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -208,6 +210,7 @@ &LITTLE_CPU_SLEEP_1
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -230,6 +233,7 @@ &LITTLE_CPU_SLEEP_1
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -252,6 +256,7 @@ &LITTLE_CPU_SLEEP_1
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -274,6 +279,7 @@ &BIG_CPU_SLEEP_1
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -296,6 +302,7 @@ &BIG_CPU_SLEEP_1
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -318,6 +325,7 @@ &BIG_CPU_SLEEP_1
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -340,6 +348,7 @@ &BIG_CPU_SLEEP_1
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

18
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file

@ -58,10 +58,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -83,6 +85,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -104,6 +107,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -125,6 +129,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -146,6 +151,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -167,6 +173,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -188,6 +195,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -209,6 +217,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -2726,6 +2735,7 @@ data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
@ -2743,6 +2753,7 @@ data-pins {
function = "dmic1_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
@ -2758,6 +2769,7 @@ data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
@ -2775,6 +2787,7 @@ data-pins {
function = "dmic2_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
@ -3982,6 +3995,7 @@ apps_rsc: rsc@18200000 {
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
label = "apps_rsc";
power-domains = <&CLUSTER_PD>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

2
arch/arm64/boot/dts/qcom/sdm630.dtsi
View file

@ -63,6 +63,7 @@ &PERF_CLUSTER_SLEEP_1
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -127,6 +128,7 @@ &PWR_CLUSTER_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

20
arch/arm64/boot/dts/qcom/sdm670.dtsi
View file

@ -41,8 +41,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
cache-level = <2>;
cache-unified;
L3_0: l3-cache {
compatible = "cache";
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -57,6 +61,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -71,6 +77,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -85,6 +93,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -99,6 +109,8 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -113,6 +125,8 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -127,6 +141,8 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -141,6 +157,8 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

13
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -108,10 +108,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -135,6 +137,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -158,6 +161,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -181,6 +185,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -204,6 +209,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -227,6 +233,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -250,6 +257,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -273,6 +281,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

2
arch/arm64/boot/dts/qcom/sm6115.dtsi
View file

@ -50,6 +50,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -102,6 +103,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/qcom/sm6125.dtsi
View file

@ -47,6 +47,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -87,6 +88,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

9
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file

@ -60,10 +60,12 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -86,6 +88,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -108,6 +111,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -130,6 +134,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -152,6 +157,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -174,6 +180,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -196,6 +203,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -218,6 +226,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

4
arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
View file

@ -178,12 +178,12 @@ &qupv3_id_1 {
};
&remoteproc_adsp {
firmware-name = "qcom/Sony/murray/adsp.mbn";
firmware-name = "qcom/sm6375/Sony/murray/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/Sony/murray/cdsp.mbn";
firmware-name = "qcom/sm6375/Sony/murray/cdsp.mbn";
status = "okay";
};

52
arch/arm64/boot/dts/qcom/sm6375.dtsi
View file

@ -48,10 +48,14 @@ CPU0: cpu@0 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -68,8 +72,10 @@ CPU1: cpu@100 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -85,8 +91,10 @@ CPU2: cpu@200 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -102,8 +110,10 @@ CPU3: cpu@300 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -119,8 +129,10 @@ CPU4: cpu@400 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -136,8 +148,10 @@ CPU5: cpu@500 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -153,8 +167,10 @@ CPU6: cpu@600 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -170,8 +186,10 @@ CPU7: cpu@700 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

13
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -63,10 +63,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -90,6 +92,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -113,6 +116,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -136,6 +140,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -159,6 +164,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -182,6 +188,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -205,6 +212,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -228,6 +236,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

2
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts
View file

@ -13,6 +13,6 @@ / {
};
&display_panel {
compatible = "xiaomi,elish-boe-nt36523";
compatible = "xiaomi,elish-boe-nt36523", "novatek,nt36523";
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts
View file

@ -13,6 +13,6 @@ / {
};
&display_panel {
compatible = "xiaomi,elish-csot-nt36523";
compatible = "xiaomi,elish-csot-nt36523", "novatek,nt36523";
status = "okay";
};

61
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file

@ -58,12 +58,14 @@ CPU0: cpu@0 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -80,9 +82,10 @@ CPU1: cpu@100 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -98,9 +101,10 @@ CPU2: cpu@200 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -116,9 +120,10 @@ CPU3: cpu@300 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -134,9 +139,10 @@ CPU4: cpu@400 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -152,9 +158,10 @@ CPU5: cpu@500 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -170,9 +177,10 @@ CPU6: cpu@600 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -188,9 +196,10 @@ CPU7: cpu@700 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

61
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file

@ -57,12 +57,14 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -79,9 +81,10 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -97,9 +100,10 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -115,9 +119,10 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -133,9 +138,10 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -151,9 +157,10 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -169,9 +176,10 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -187,9 +195,10 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};

26
arch/arm64/boot/dts/qcom/sm8550.dtsi
View file

@ -80,10 +80,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
@ -104,6 +106,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -124,6 +127,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -144,6 +148,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -164,6 +169,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -184,6 +190,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -204,6 +211,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -224,6 +232,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
@ -2022,7 +2031,7 @@ swr3: soundwire-controller@6ab0000 {
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
@ -2068,7 +2077,7 @@ swr1: soundwire-controller@6ad0000 {
qcom,din-ports = <0>;
qcom,dout-ports = <10>;
qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
@ -2133,7 +2142,7 @@ swr0: soundwire-controller@6b10000 {
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
@ -3762,9 +3771,16 @@ gem_noc: interconnect@24100000 {
system-cache-controller@25000000 {
compatible = "qcom,sm8550-llcc";
reg = <0 0x25000000 0 0x800000>,
reg = <0 0x25000000 0 0x200000>,
<0 0x25200000 0 0x200000>,
<0 0x25400000 0 0x200000>,
<0 0x25600000 0 0x200000>,
<0 0x25800000 0 0x200000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
"llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};

3
arch/arm64/mm/fault.c
View file

@ -600,8 +600,7 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr,
vma_end_read(vma);
goto lock_mmap;
}
fault = handle_mm_fault(vma, addr & PAGE_MASK,
mm_flags | FAULT_FLAG_VMA_LOCK, regs);
fault = handle_mm_fault(vma, addr, mm_flags | FAULT_FLAG_VMA_LOCK, regs);
vma_end_read(vma);
if (!(fault & VM_FAULT_RETRY)) {

2
arch/loongarch/include/asm/loongarch.h
View file

@ -1496,7 +1496,7 @@ __BUILD_CSR_OP(tlbidx)
#define write_fcsr(dest, val) \
do { \
__asm__ __volatile__( \
" movgr2fcsr %0, "__stringify(dest)" \n" \
" movgr2fcsr "__stringify(dest)", %0 \n" \
: : "r" (val)); \
} while (0)

2
arch/loongarch/include/asm/pgtable-bits.h
View file

@ -22,12 +22,14 @@
#define _PAGE_PFN_SHIFT 12
#define _PAGE_SWP_EXCLUSIVE_SHIFT 23
#define _PAGE_PFN_END_SHIFT 48
#define _PAGE_PRESENT_INVALID_SHIFT 60
#define _PAGE_NO_READ_SHIFT 61
#define _PAGE_NO_EXEC_SHIFT 62
#define _PAGE_RPLV_SHIFT 63
/* Used by software */
#define _PAGE_PRESENT (_ULCAST_(1) << _PAGE_PRESENT_SHIFT)
#define _PAGE_PRESENT_INVALID (_ULCAST_(1) << _PAGE_PRESENT_INVALID_SHIFT)
#define _PAGE_WRITE (_ULCAST_(1) << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED (_ULCAST_(1) << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED (_ULCAST_(1) << _PAGE_MODIFIED_SHIFT)

3
arch/loongarch/include/asm/pgtable.h
View file

@ -213,7 +213,7 @@ static inline int pmd_bad(pmd_t pmd)
static inline int pmd_present(pmd_t pmd)
{
if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
return !!(pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE));
return !!(pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PRESENT_INVALID));
return pmd_val(pmd) != (unsigned long)invalid_pte_table;
}
@ -558,6 +558,7 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
static inline pmd_t pmd_mkinvalid(pmd_t pmd)
{
pmd_val(pmd) |= _PAGE_PRESENT_INVALID;
pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY | _PAGE_PROTNONE);
return pmd;

2
arch/loongarch/kernel/hw_breakpoint.c
View file

@ -396,6 +396,8 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
if (hw->ctrl.type != LOONGARCH_BREAKPOINT_EXECUTE)
alignment_mask = 0x7;
else
alignment_mask = 0x3;
offset = hw->address & alignment_mask;
hw->address &= ~alignment_mask;

6
arch/loongarch/kernel/perf_event.c
View file

@ -271,7 +271,7 @@ static void loongarch_pmu_enable_event(struct hw_perf_event *evt, int idx)
WARN_ON(idx < 0 || idx >= loongarch_pmu.num_counters);
/* Make sure interrupt enabled. */
cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base) |
(evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE;
cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
@ -594,7 +594,7 @@ static struct pmu pmu = {
static unsigned int loongarch_pmu_perf_event_encode(const struct loongarch_perf_event *pev)
{
return (pev->event_id & 0xff);
return M_PERFCTL_EVENT(pev->event_id);
}
static const struct loongarch_perf_event *loongarch_pmu_map_general_event(int idx)
@ -849,7 +849,7 @@ static void resume_local_counters(void)
static const struct loongarch_perf_event *loongarch_pmu_map_raw_event(u64 config)
{
raw_event.event_id = config & 0xff;
raw_event.event_id = M_PERFCTL_EVENT(config);
return &raw_event;
}

2
arch/loongarch/kernel/unaligned.c
View file

@ -485,7 +485,7 @@ static int __init debugfs_unaligned(void)
struct dentry *d;
d = debugfs_create_dir("loongarch", NULL);
if (!d)
if (IS_ERR_OR_NULL(d))
return -ENOMEM;
debugfs_create_u32("unaligned_instructions_user",

2
arch/nios2/boot/dts/10m50_devboard.dts
View file

@ -97,7 +97,7 @@ rgmii_0_eth_tse_0: ethernet@400 {
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
address-bits = <48>;
max-frame-size = <1518>;
max-frame-size = <1500>;
local-mac-address = [00 00 00 00 00 00];
altr,has-supplementary-unicast;
altr,enable-sup-addr = <1>;

2
arch/nios2/boot/dts/3c120_devboard.dts
View file

@ -106,7 +106,7 @@ tse_mac: ethernet@4000 {
interrupt-names = "rx_irq", "tx_irq";
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
max-frame-size = <1518>;
max-frame-size = <1500>;
local-mac-address = [ 00 00 00 00 00 00 ];
phy-mode = "rgmii-id";
phy-handle = <&phy0>;

5
arch/powerpc/purgatory/Makefile
View file

@ -5,6 +5,11 @@ KCSAN_SANITIZE := n
targets += trampoline_$(BITS).o purgatory.ro
# When profile-guided optimization is enabled, llvm emits two different
# overlapping text sections, which is not supported by kexec. Remove profile
# optimization flags.
KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%,$(KBUILD_CFLAGS))
LDFLAGS_purgatory.ro := -e purgatory_start -r --no-undefined
$(obj)/purgatory.ro: $(obj)/trampoline_$(BITS).o FORCE

1
arch/riscv/Kconfig
View file

@ -26,6 +26,7 @@ config RISCV
select ARCH_HAS_GIGANTIC_PAGE
select ARCH_HAS_KCOV
select ARCH_HAS_MMIOWB
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PMEM_API
select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SET_DIRECT_MAP if MMU

33
arch/riscv/include/asm/kfence.h
View file

@ -8,41 +8,8 @@
#include <asm-generic/pgalloc.h>
#include <asm/pgtable.h>
static inline int split_pmd_page(unsigned long addr)
{
int i;
unsigned long pfn = PFN_DOWN(__pa((addr & PMD_MASK)));
pmd_t *pmd = pmd_off_k(addr);
pte_t *pte = pte_alloc_one_kernel(&init_mm);
if (!pte)
return -ENOMEM;
for (i = 0; i < PTRS_PER_PTE; i++)
set_pte(pte + i, pfn_pte(pfn + i, PAGE_KERNEL));
set_pmd(pmd, pfn_pmd(PFN_DOWN(__pa(pte)), PAGE_TABLE));
flush_tlb_kernel_range(addr, addr + PMD_SIZE);
return 0;
}
static inline bool arch_kfence_init_pool(void)
{
int ret;
unsigned long addr;
pmd_t *pmd;
for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr);
addr += PAGE_SIZE) {
pmd = pmd_off_k(addr);
if (pmd_leaf(*pmd)) {
ret = split_pmd_page(addr);
if (ret)
return false;
}
}
return true;
}

3
arch/riscv/include/asm/pgtable.h
View file

@ -165,8 +165,7 @@ extern struct pt_alloc_ops pt_ops __initdata;
_PAGE_EXEC | _PAGE_WRITE)
#define PAGE_COPY PAGE_READ
#define PAGE_COPY_EXEC PAGE_EXEC
#define PAGE_COPY_READ_EXEC PAGE_READ_EXEC
#define PAGE_COPY_EXEC PAGE_READ_EXEC
#define PAGE_SHARED PAGE_WRITE
#define PAGE_SHARED_EXEC PAGE_WRITE_EXEC

48
arch/riscv/mm/init.c
View file

@ -23,6 +23,7 @@
#ifdef CONFIG_RELOCATABLE
#include <linux/elf.h>
#endif
#include <linux/kfence.h>
#include <asm/fixmap.h>
#include <asm/tlbflush.h>
@ -293,7 +294,7 @@ static const pgprot_t protection_map[16] = {
[VM_EXEC] = PAGE_EXEC,
[VM_EXEC | VM_READ] = PAGE_READ_EXEC,
[VM_EXEC | VM_WRITE] = PAGE_COPY_EXEC,
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_READ_EXEC,
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_EXEC,
[VM_SHARED] = PAGE_NONE,
[VM_SHARED | VM_READ] = PAGE_READ,
[VM_SHARED | VM_WRITE] = PAGE_SHARED,
@ -659,18 +660,19 @@ void __init create_pgd_mapping(pgd_t *pgdp,
create_pgd_next_mapping(nextp, va, pa, sz, prot);
}
static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size)
static uintptr_t __init best_map_size(phys_addr_t pa, uintptr_t va,
phys_addr_t size)
{
if (!(base & (PGDIR_SIZE - 1)) && size >= PGDIR_SIZE)
if (!(pa & (PGDIR_SIZE - 1)) && !(va & (PGDIR_SIZE - 1)) && size >= PGDIR_SIZE)
return PGDIR_SIZE;
if (!(base & (P4D_SIZE - 1)) && size >= P4D_SIZE)
if (!(pa & (P4D_SIZE - 1)) && !(va & (P4D_SIZE - 1)) && size >= P4D_SIZE)
return P4D_SIZE;
if (!(base & (PUD_SIZE - 1)) && size >= PUD_SIZE)
if (!(pa & (PUD_SIZE - 1)) && !(va & (PUD_SIZE - 1)) && size >= PUD_SIZE)
return PUD_SIZE;
if (!(base & (PMD_SIZE - 1)) && size >= PMD_SIZE)
if (!(pa & (PMD_SIZE - 1)) && !(va & (PMD_SIZE - 1)) && size >= PMD_SIZE)
return PMD_SIZE;
return PAGE_SIZE;
@ -1167,14 +1169,16 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
}
static void __init create_linear_mapping_range(phys_addr_t start,
phys_addr_t end)
phys_addr_t end,
uintptr_t fixed_map_size)
{
phys_addr_t pa;
uintptr_t va, map_size;
for (pa = start; pa < end; pa += map_size) {
va = (uintptr_t)__va(pa);
map_size = best_map_size(pa, end - pa);
map_size = fixed_map_size ? fixed_map_size :
best_map_size(pa, va, end - pa);
create_pgd_mapping(swapper_pg_dir, va, pa, map_size,
pgprot_from_va(va));
@ -1184,6 +1188,7 @@ static void __init create_linear_mapping_range(phys_addr_t start,
static void __init create_linear_mapping_page_table(void)
{
phys_addr_t start, end;
phys_addr_t kfence_pool __maybe_unused;
u64 i;
#ifdef CONFIG_STRICT_KERNEL_RWX
@ -1197,6 +1202,19 @@ static void __init create_linear_mapping_page_table(void)
memblock_mark_nomap(krodata_start, krodata_size);
#endif
#ifdef CONFIG_KFENCE
/*
* kfence pool must be backed by PAGE_SIZE mappings, so allocate it
* before we setup the linear mapping so that we avoid using hugepages
* for this region.
*/
kfence_pool = memblock_phys_alloc(KFENCE_POOL_SIZE, PAGE_SIZE);
BUG_ON(!kfence_pool);
memblock_mark_nomap(kfence_pool, KFENCE_POOL_SIZE);
__kfence_pool = __va(kfence_pool);
#endif
/* Map all memory banks in the linear mapping */
for_each_mem_range(i, &start, &end) {
if (start >= end)
@ -1207,17 +1225,25 @@ static void __init create_linear_mapping_page_table(void)
if (end >= __pa(PAGE_OFFSET) + memory_limit)
end = __pa(PAGE_OFFSET) + memory_limit;
create_linear_mapping_range(start, end);
create_linear_mapping_range(start, end, 0);
}
#ifdef CONFIG_STRICT_KERNEL_RWX
create_linear_mapping_range(ktext_start, ktext_start + ktext_size);
create_linear_mapping_range(ktext_start, ktext_start + ktext_size, 0);
create_linear_mapping_range(krodata_start,
krodata_start + krodata_size);
krodata_start + krodata_size, 0);
memblock_clear_nomap(ktext_start, ktext_size);
memblock_clear_nomap(krodata_start, krodata_size);
#endif
#ifdef CONFIG_KFENCE
create_linear_mapping_range(kfence_pool,
kfence_pool + KFENCE_POOL_SIZE,
PAGE_SIZE);
memblock_clear_nomap(kfence_pool, KFENCE_POOL_SIZE);
#endif
}
static void __init setup_vm_final(void)

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