mirror of
https://github.com/torvalds/linux
synced 2024-09-21 03:28:37 +00:00
Merge branch 'pm-tools'
* pm-tools: cpupower: Add support for new AMD family 0x17 cpupower: Fix bug where return value was not used tools/power turbostat: update version number tools/power turbostat: decode MSR_IA32_MISC_ENABLE only on Intel tools/power turbostat: stop migrating, unless '-m' tools/power turbostat: if --debug, print sampling overhead tools/power turbostat: hide SKL counters, when not requested intel_pstate: use updated msr-index.h HWP.EPP values tools/power x86_energy_perf_policy: support HWP.EPP x86: msr-index.h: fix shifts to ULL results in HWP macros. x86: msr-index.h: define HWP.EPP values x86: msr-index.h: define EPB mid-points
This commit is contained in:
Rafael J. Wysocki
commit
16b5b09240
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@ -249,9 +249,13 @@
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#define HWP_MIN_PERF(x) (x & 0xff)
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#define HWP_MAX_PERF(x) ((x & 0xff) << 8)
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#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
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#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24)
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#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32)
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#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)
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#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
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#define HWP_EPP_PERFORMANCE 0x00
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#define HWP_EPP_BALANCE_PERFORMANCE 0x80
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#define HWP_EPP_BALANCE_POWERSAVE 0xC0
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#define HWP_EPP_POWERSAVE 0xFF
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#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
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#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
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/* IA32_HWP_STATUS */
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#define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
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@ -474,9 +478,11 @@
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#define MSR_MISC_PWR_MGMT 0x000001aa
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
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#define ENERGY_PERF_BIAS_PERFORMANCE 0
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#define ENERGY_PERF_BIAS_NORMAL 6
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#define ENERGY_PERF_BIAS_POWERSAVE 15
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#define ENERGY_PERF_BIAS_PERFORMANCE 0
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#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
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#define ENERGY_PERF_BIAS_NORMAL 6
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#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
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#define ENERGY_PERF_BIAS_POWERSAVE 15
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#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
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@ -653,6 +653,12 @@ static const char * const energy_perf_strings[] = {
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"power",
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NULL
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};
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static const unsigned int epp_values[] = {
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HWP_EPP_PERFORMANCE,
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HWP_EPP_BALANCE_PERFORMANCE,
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HWP_EPP_BALANCE_POWERSAVE,
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HWP_EPP_POWERSAVE
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};
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static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
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{
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@ -664,17 +670,14 @@ static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
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return epp;
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if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
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/*
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* Range:
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* 0x00-0x3F : Performance
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* 0x40-0x7F : Balance performance
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* 0x80-0xBF : Balance power
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* 0xC0-0xFF : Power
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* The EPP is a 8 bit value, but our ranges restrict the
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* value which can be set. Here only using top two bits
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* effectively.
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*/
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index = (epp >> 6) + 1;
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if (epp == HWP_EPP_PERFORMANCE)
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return 1;
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if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
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return 2;
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if (epp <= HWP_EPP_BALANCE_POWERSAVE)
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return 3;
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else
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return 4;
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} else if (static_cpu_has(X86_FEATURE_EPB)) {
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/*
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* Range:
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@ -712,15 +715,8 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
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value &= ~GENMASK_ULL(31, 24);
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/*
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* If epp is not default, convert from index into
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* energy_perf_strings to epp value, by shifting 6
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* bits left to use only top two bits in epp.
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* The resultant epp need to shifted by 24 bits to
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* epp position in MSR_HWP_REQUEST.
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*/
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if (epp == -EINVAL)
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epp = (pref_index - 1) << 6;
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epp = epp_values[pref_index - 1];
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value |= (u64)epp << 24;
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ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
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@ -26,6 +26,15 @@ union msr_pstate {
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unsigned res3:21;
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unsigned en:1;
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} bits;
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struct {
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unsigned fid:8;
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unsigned did:6;
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unsigned vid:8;
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unsigned iddval:8;
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unsigned idddiv:2;
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unsigned res1:30;
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unsigned en:1;
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} fam17h_bits;
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unsigned long long val;
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};
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@ -35,6 +44,8 @@ static int get_did(int family, union msr_pstate pstate)
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if (family == 0x12)
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t = pstate.val & 0xf;
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else if (family == 0x17)
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t = pstate.fam17h_bits.did;
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else
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t = pstate.bits.did;
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@ -44,16 +55,20 @@ static int get_did(int family, union msr_pstate pstate)
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static int get_cof(int family, union msr_pstate pstate)
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{
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int t;
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int fid, did;
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int fid, did, cof;
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did = get_did(family, pstate);
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t = 0x10;
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fid = pstate.bits.fid;
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if (family == 0x11)
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t = 0x8;
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return (100 * (fid + t)) >> did;
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if (family == 0x17) {
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fid = pstate.fam17h_bits.fid;
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cof = 200 * fid / did;
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} else {
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t = 0x10;
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fid = pstate.bits.fid;
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if (family == 0x11)
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t = 0x8;
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cof = (100 * (fid + t)) >> did;
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}
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return cof;
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}
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/* Needs:
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@ -70,6 +70,8 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
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#define CPUPOWER_CAP_IS_SNB 0x00000020
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#define CPUPOWER_CAP_INTEL_IDA 0x00000040
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#define CPUPOWER_AMD_CPBDIS 0x02000000
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#define MAX_HW_PSTATES 10
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struct cpupower_cpu_info {
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@ -2,11 +2,14 @@
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#include "helpers/helpers.h"
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#define MSR_AMD_HWCR 0xc0010015
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int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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int *states)
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{
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struct cpupower_cpu_info cpu_info;
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int ret;
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unsigned long long val;
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*support = *active = *states = 0;
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@ -16,10 +19,22 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
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*support = 1;
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amd_pci_get_num_boost_states(active, states);
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if (ret <= 0)
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return ret;
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*support = 1;
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/* AMD Family 0x17 does not utilize PCI D18F4 like prior
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* families and has no fixed discrete boost states but
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* has Hardware determined variable increments instead.
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*/
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if (cpu_info.family == 0x17) {
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if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
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if (!(val & CPUPOWER_AMD_CPBDIS))
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*active = 1;
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}
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} else {
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ret = amd_pci_get_num_boost_states(active, states);
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if (ret)
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return ret;
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}
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} else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
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*support = *active = 1;
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return 0;
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@ -57,7 +57,6 @@ unsigned int list_header_only;
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unsigned int dump_only;
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unsigned int do_snb_cstates;
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unsigned int do_knl_cstates;
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unsigned int do_skl_residency;
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unsigned int do_slm_cstates;
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unsigned int use_c1_residency_msr;
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unsigned int has_aperf;
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@ -93,6 +92,7 @@ unsigned int do_ring_perf_limit_reasons;
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unsigned int crystal_hz;
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unsigned long long tsc_hz;
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int base_cpu;
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int do_migrate;
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double discover_bclk(unsigned int family, unsigned int model);
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unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
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/* IA32_HWP_REQUEST, IA32_HWP_STATUS */
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@ -151,6 +151,8 @@ size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
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#define MAX_ADDED_COUNTERS 16
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struct thread_data {
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struct timeval tv_begin;
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struct timeval tv_end;
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unsigned long long tsc;
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unsigned long long aperf;
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unsigned long long mperf;
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@ -301,6 +303,9 @@ int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg
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int cpu_migrate(int cpu)
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{
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if (!do_migrate)
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return 0;
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CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
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CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
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if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
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@ -384,8 +389,14 @@ struct msr_counter bic[] = {
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{ 0x0, "CPU" },
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{ 0x0, "Mod%c6" },
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{ 0x0, "sysfs" },
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{ 0x0, "Totl%C0" },
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{ 0x0, "Any%C0" },
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{ 0x0, "GFX%C0" },
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{ 0x0, "CPUGFX%" },
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};
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#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
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#define BIC_Package (1ULL << 0)
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#define BIC_Avg_MHz (1ULL << 1)
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@ -426,6 +437,10 @@ struct msr_counter bic[] = {
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#define BIC_CPU (1ULL << 36)
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#define BIC_Mod_c6 (1ULL << 37)
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#define BIC_sysfs (1ULL << 38)
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#define BIC_Totl_c0 (1ULL << 39)
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#define BIC_Any_c0 (1ULL << 40)
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#define BIC_GFX_c0 (1ULL << 41)
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#define BIC_CPUGFX (1ULL << 42)
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unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
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unsigned long long bic_present = BIC_sysfs;
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@ -521,6 +536,8 @@ void print_header(char *delim)
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struct msr_counter *mp;
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int printed = 0;
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if (debug)
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outp += sprintf(outp, "usec %s", delim);
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if (DO_BIC(BIC_Package))
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outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
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if (DO_BIC(BIC_Core))
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@ -599,12 +616,14 @@ void print_header(char *delim)
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if (DO_BIC(BIC_GFXMHz))
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outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
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if (do_skl_residency) {
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if (DO_BIC(BIC_Totl_c0))
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outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
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if (DO_BIC(BIC_Any_c0))
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outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
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if (DO_BIC(BIC_GFX_c0))
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outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
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if (DO_BIC(BIC_CPUGFX))
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outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
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}
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if (DO_BIC(BIC_Pkgpc2))
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outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
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@ -771,6 +790,14 @@ int format_counters(struct thread_data *t, struct core_data *c,
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(cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
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return 0;
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if (debug) {
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/* on each row, print how many usec each timestamp took to gather */
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struct timeval tv;
|
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|
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timersub(&t->tv_end, &t->tv_begin, &tv);
|
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outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
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}
|
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|
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interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
|
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|
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tsc = t->tsc * tsc_tweak;
|
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|
|
@ -912,12 +939,14 @@ int format_counters(struct thread_data *t, struct core_data *c,
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outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
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||||
|
||||
/* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
|
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if (do_skl_residency) {
|
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if (DO_BIC(BIC_Totl_c0))
|
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outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc);
|
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if (DO_BIC(BIC_Any_c0))
|
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outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc);
|
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if (DO_BIC(BIC_GFX_c0))
|
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outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc);
|
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if (DO_BIC(BIC_CPUGFX))
|
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outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc);
|
||||
}
|
||||
|
||||
if (DO_BIC(BIC_Pkgpc2))
|
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outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc);
|
||||
|
|
@ -1038,12 +1067,16 @@ delta_package(struct pkg_data *new, struct pkg_data *old)
|
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int i;
|
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struct msr_counter *mp;
|
||||
|
||||
if (do_skl_residency) {
|
||||
|
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if (DO_BIC(BIC_Totl_c0))
|
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old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
|
||||
if (DO_BIC(BIC_Any_c0))
|
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old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
|
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if (DO_BIC(BIC_GFX_c0))
|
||||
old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
|
||||
if (DO_BIC(BIC_CPUGFX))
|
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old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
|
||||
}
|
||||
|
||||
old->pc2 = new->pc2 - old->pc2;
|
||||
if (DO_BIC(BIC_Pkgpc3))
|
||||
old->pc3 = new->pc3 - old->pc3;
|
||||
|
|
@ -1292,12 +1325,14 @@ int sum_counters(struct thread_data *t, struct core_data *c,
|
|||
if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
|
||||
return 0;
|
||||
|
||||
if (do_skl_residency) {
|
||||
if (DO_BIC(BIC_Totl_c0))
|
||||
average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
|
||||
if (DO_BIC(BIC_Any_c0))
|
||||
average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
|
||||
if (DO_BIC(BIC_GFX_c0))
|
||||
average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
|
||||
if (DO_BIC(BIC_CPUGFX))
|
||||
average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
|
||||
}
|
||||
|
||||
average.packages.pc2 += p->pc2;
|
||||
if (DO_BIC(BIC_Pkgpc3))
|
||||
|
|
@ -1357,12 +1392,14 @@ void compute_average(struct thread_data *t, struct core_data *c,
|
|||
average.cores.c7 /= topo.num_cores;
|
||||
average.cores.mc6_us /= topo.num_cores;
|
||||
|
||||
if (do_skl_residency) {
|
||||
if (DO_BIC(BIC_Totl_c0))
|
||||
average.packages.pkg_wtd_core_c0 /= topo.num_packages;
|
||||
if (DO_BIC(BIC_Any_c0))
|
||||
average.packages.pkg_any_core_c0 /= topo.num_packages;
|
||||
if (DO_BIC(BIC_GFX_c0))
|
||||
average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
|
||||
if (DO_BIC(BIC_CPUGFX))
|
||||
average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
|
||||
}
|
||||
|
||||
average.packages.pc2 /= topo.num_packages;
|
||||
if (DO_BIC(BIC_Pkgpc3))
|
||||
|
|
@ -1482,6 +1519,9 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
|
|||
struct msr_counter *mp;
|
||||
int i;
|
||||
|
||||
|
||||
gettimeofday(&t->tv_begin, (struct timezone *)NULL);
|
||||
|
||||
if (cpu_migrate(cpu)) {
|
||||
fprintf(outf, "Could not migrate to CPU %d\n", cpu);
|
||||
return -1;
|
||||
|
|
@ -1565,7 +1605,7 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
|
|||
|
||||
/* collect core counters only for 1st thread in core */
|
||||
if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
|
||||
return 0;
|
||||
goto done;
|
||||
|
||||
if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
|
||||
if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
|
||||
|
|
@ -1601,15 +1641,21 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
|
|||
|
||||
/* collect package counters only for 1st core in package */
|
||||
if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
|
||||
return 0;
|
||||
goto done;
|
||||
|
||||
if (do_skl_residency) {
|
||||
if (DO_BIC(BIC_Totl_c0)) {
|
||||
if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
|
||||
return -10;
|
||||
}
|
||||
if (DO_BIC(BIC_Any_c0)) {
|
||||
if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
|
||||
return -11;
|
||||
}
|
||||
if (DO_BIC(BIC_GFX_c0)) {
|
||||
if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
|
||||
return -12;
|
||||
}
|
||||
if (DO_BIC(BIC_CPUGFX)) {
|
||||
if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
|
||||
return -13;
|
||||
}
|
||||
|
|
@ -1688,6 +1734,8 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
|
|||
if (get_mp(cpu, mp, &p->counter[i]))
|
||||
return -10;
|
||||
}
|
||||
done:
|
||||
gettimeofday(&t->tv_end, (struct timezone *)NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -3895,6 +3943,9 @@ void decode_misc_enable_msr(void)
|
|||
{
|
||||
unsigned long long msr;
|
||||
|
||||
if (!genuine_intel)
|
||||
return;
|
||||
|
||||
if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
|
||||
fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
|
||||
base_cpu, msr,
|
||||
|
|
@ -4198,7 +4249,12 @@ void process_cpuid()
|
|||
BIC_PRESENT(BIC_Pkgpc10);
|
||||
}
|
||||
do_irtl_hsw = has_hsw_msrs(family, model);
|
||||
do_skl_residency = has_skl_msrs(family, model);
|
||||
if (has_skl_msrs(family, model)) {
|
||||
BIC_PRESENT(BIC_Totl_c0);
|
||||
BIC_PRESENT(BIC_Any_c0);
|
||||
BIC_PRESENT(BIC_GFX_c0);
|
||||
BIC_PRESENT(BIC_CPUGFX);
|
||||
}
|
||||
do_slm_cstates = is_slm(family, model);
|
||||
do_knl_cstates = is_knl(family, model);
|
||||
|
||||
|
|
@ -4578,7 +4634,7 @@ int get_and_dump_counters(void)
|
|||
}
|
||||
|
||||
void print_version() {
|
||||
fprintf(outf, "turbostat version 17.04.12"
|
||||
fprintf(outf, "turbostat version 17.06.23"
|
||||
" - Len Brown <lenb@kernel.org>\n");
|
||||
}
|
||||
|
||||
|
|
@ -4951,6 +5007,7 @@ void cmdline(int argc, char **argv)
|
|||
{"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
|
||||
{"Joules", no_argument, 0, 'J'},
|
||||
{"list", no_argument, 0, 'l'},
|
||||
{"migrate", no_argument, 0, 'm'},
|
||||
{"out", required_argument, 0, 'o'},
|
||||
{"quiet", no_argument, 0, 'q'},
|
||||
{"show", required_argument, 0, 's'},
|
||||
|
|
@ -4962,7 +5019,7 @@ void cmdline(int argc, char **argv)
|
|||
|
||||
progname = argv[0];
|
||||
|
||||
while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:qST:v",
|
||||
while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:Jmo:qST:v",
|
||||
long_options, &option_index)) != -1) {
|
||||
switch (opt) {
|
||||
case 'a':
|
||||
|
|
@ -5005,6 +5062,9 @@ void cmdline(int argc, char **argv)
|
|||
list_header_only++;
|
||||
quiet++;
|
||||
break;
|
||||
case 'm':
|
||||
do_migrate = 1;
|
||||
break;
|
||||
case 'o':
|
||||
outf = fopen_or_die(optarg, "w");
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,10 +1,27 @@
|
|||
DESTDIR ?=
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
BUILD_OUTPUT := $(CURDIR)
|
||||
PREFIX := /usr
|
||||
DESTDIR :=
|
||||
|
||||
ifeq ("$(origin O)", "command line")
|
||||
BUILD_OUTPUT := $(O)
|
||||
endif
|
||||
|
||||
x86_energy_perf_policy : x86_energy_perf_policy.c
|
||||
CFLAGS += -Wall
|
||||
CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
|
||||
|
||||
%: %.c
|
||||
@mkdir -p $(BUILD_OUTPUT)
|
||||
$(CC) $(CFLAGS) $< -o $(BUILD_OUTPUT)/$@
|
||||
|
||||
.PHONY : clean
|
||||
clean :
|
||||
rm -f x86_energy_perf_policy
|
||||
@rm -f $(BUILD_OUTPUT)/x86_energy_perf_policy
|
||||
|
||||
install : x86_energy_perf_policy
|
||||
install -d $(DESTDIR)$(PREFIX)/bin
|
||||
install $(BUILD_OUTPUT)/x86_energy_perf_policy $(DESTDIR)$(PREFIX)/bin/x86_energy_perf_policy
|
||||
install -d $(DESTDIR)$(PREFIX)/share/man/man8
|
||||
install x86_energy_perf_policy.8 $(DESTDIR)$(PREFIX)/share/man/man8
|
||||
|
||||
install :
|
||||
install x86_energy_perf_policy ${DESTDIR}/usr/bin/
|
||||
install x86_energy_perf_policy.8 ${DESTDIR}/usr/share/man/man8/
|
||||
|
|
|
|||
|
|
@ -1,104 +1,213 @@
|
|||
.\" This page Copyright (C) 2010 Len Brown <len.brown@intel.com>
|
||||
.\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
|
||||
.\" Distributed under the GPL, Copyleft 1994.
|
||||
.TH X86_ENERGY_PERF_POLICY 8
|
||||
.SH NAME
|
||||
x86_energy_perf_policy \- read or write MSR_IA32_ENERGY_PERF_BIAS
|
||||
x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
|
||||
.SH SYNOPSIS
|
||||
.ft B
|
||||
.B x86_energy_perf_policy
|
||||
.RB [ "\-c cpu" ]
|
||||
.RB [ "\-v" ]
|
||||
.RB "\-r"
|
||||
.RB "[ options ] [ scope ] [field \ value]"
|
||||
.br
|
||||
.B x86_energy_perf_policy
|
||||
.RB [ "\-c cpu" ]
|
||||
.RB [ "\-v" ]
|
||||
.RB 'performance'
|
||||
.RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
|
||||
.br
|
||||
.B x86_energy_perf_policy
|
||||
.RB [ "\-c cpu" ]
|
||||
.RB [ "\-v" ]
|
||||
.RB 'normal'
|
||||
.RB "cpu-list, pkg-list: # | #,# | #-# | all"
|
||||
.br
|
||||
.B x86_energy_perf_policy
|
||||
.RB [ "\-c cpu" ]
|
||||
.RB [ "\-v" ]
|
||||
.RB 'powersave'
|
||||
.RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
|
||||
.br
|
||||
.B x86_energy_perf_policy
|
||||
.RB [ "\-c cpu" ]
|
||||
.RB [ "\-v" ]
|
||||
.RB n
|
||||
.RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
|
||||
.br
|
||||
.RB "value: # | default | performance | balance-performance | balance-power | power"
|
||||
.SH DESCRIPTION
|
||||
\fBx86_energy_perf_policy\fP
|
||||
allows software to convey
|
||||
its policy for the relative importance of performance
|
||||
versus energy savings to the processor.
|
||||
displays and updates energy-performance policy settings specific to
|
||||
Intel Architecture Processors. Settings are accessed via Model Specific Register (MSR)
|
||||
updates, no matter if the Linux cpufreq sub-system is enabled or not.
|
||||
|
||||
The processor uses this information in model-specific ways
|
||||
when it must select trade-offs between performance and
|
||||
energy efficiency.
|
||||
Policy in MSR_IA32_ENERGY_PERF_BIAS (EPB)
|
||||
may affect a wide range of hardware decisions,
|
||||
such as how aggressively the hardware enters and exits CPU idle states (C-states)
|
||||
and Processor Performance States (P-states).
|
||||
This policy hint does not replace explicit OS C-state and P-state selection.
|
||||
Rather, it tells the hardware how aggressively to implement those selections.
|
||||
Further, it allows the OS to influence energy/performance trade-offs where there
|
||||
is no software interface, such as in the opportunistic "turbo-mode" P-state range.
|
||||
Note that MSR_IA32_ENERGY_PERF_BIAS is defined per CPU,
|
||||
but some implementations
|
||||
share a single MSR among all CPUs in each processor package.
|
||||
On those systems, a write to EPB on one processor will
|
||||
be visible, and will have an effect, on all CPUs
|
||||
in the same processor package.
|
||||
|
||||
This policy hint does not supersede Processor Performance states
|
||||
(P-states) or CPU Idle power states (C-states), but allows
|
||||
software to have influence where it would otherwise be unable
|
||||
to express a preference.
|
||||
Hardware P-States (HWP) are effectively an expansion of hardware
|
||||
P-state control from the opportunistic turbo-mode P-state range
|
||||
to include the entire range of available P-states.
|
||||
On Broadwell Xeon, the initial HWP implementation, EBP influenced HWP.
|
||||
That influence was removed in subsequent generations,
|
||||
where it was moved to the
|
||||
Energy_Performance_Preference (EPP) field in
|
||||
a pair of dedicated MSRs -- MSR_IA32_HWP_REQUEST and MSR_IA32_HWP_REQUEST_PKG.
|
||||
|
||||
For example, this setting may tell the hardware how
|
||||
aggressively or conservatively to control frequency
|
||||
in the "turbo range" above the explicitly OS-controlled
|
||||
P-state frequency range. It may also tell the hardware
|
||||
how aggressively is should enter the OS requested C-states.
|
||||
EPP is the most commonly managed knob in HWP mode,
|
||||
but MSR_IA32_HWP_REQUEST also allows the user to specify
|
||||
minimum-frequency for Quality-of-Service,
|
||||
and maximum-frequency for power-capping.
|
||||
MSR_IA32_HWP_REQUEST is defined per-CPU.
|
||||
|
||||
Support for this feature is indicated by CPUID.06H.ECX.bit3
|
||||
per the Intel Architectures Software Developer's Manual.
|
||||
MSR_IA32_HWP_REQUEST_PKG has the same capability as MSR_IA32_HWP_REQUEST,
|
||||
but it can simultaneously set the default policy for all CPUs within a package.
|
||||
A bit in per-CPU MSR_IA32_HWP_REQUEST indicates whether it is
|
||||
over-ruled-by or exempt-from MSR_IA32_HWP_REQUEST_PKG.
|
||||
|
||||
.SS Options
|
||||
\fB-c\fP limits operation to a single CPU.
|
||||
The default is to operate on all CPUs.
|
||||
Note that MSR_IA32_ENERGY_PERF_BIAS is defined per
|
||||
logical processor, but that the initial implementations
|
||||
of the MSR were shared among all processors in each package.
|
||||
MSR_HWP_CAPABILITIES shows the default values for the fields
|
||||
in MSR_IA32_HWP_REQUEST. It is displayed when no values
|
||||
are being written.
|
||||
|
||||
.SS SCOPE OPTIONS
|
||||
.PP
|
||||
\fB-v\fP increases verbosity. By default
|
||||
x86_energy_perf_policy is silent.
|
||||
\fB-c, --cpu\fP Operate on the MSR_IA32_HWP_REQUEST for each CPU in a CPU-list.
|
||||
The CPU-list may be comma-separated CPU numbers, with dash for range
|
||||
or the string "all". Eg. '--cpu 1,4,6-8' or '--cpu all'.
|
||||
When --cpu is used, \fB--hwp-use-pkg\fP is available, which specifies whether the per-cpu
|
||||
MSR_IA32_HWP_REQUEST should be over-ruled by MSR_IA32_HWP_REQUEST_PKG (1),
|
||||
or exempt from MSR_IA32_HWP_REQUEST_PKG (0).
|
||||
|
||||
\fB-p, --pkg\fP Operate on the MSR_IA32_HWP_REQUEST_PKG for each package in the package-list.
|
||||
The list is a string of individual package numbers separated
|
||||
by commas, and or ranges of package numbers separated by a dash,
|
||||
or the string "all".
|
||||
For example '--pkg 1,3' or '--pkg all'
|
||||
|
||||
.SS VALUE OPTIONS
|
||||
.PP
|
||||
\fB-r\fP is for "read-only" mode - the unchanged state
|
||||
is read and displayed.
|
||||
.PP
|
||||
.I performance
|
||||
Set a policy where performance is paramount.
|
||||
The processor will be unwilling to sacrifice any performance
|
||||
for the sake of energy saving. This is the hardware default.
|
||||
.PP
|
||||
.I normal
|
||||
.I normal | default
|
||||
Set a policy with a normal balance between performance and energy efficiency.
|
||||
The processor will tolerate minor performance compromise
|
||||
for potentially significant energy savings.
|
||||
This reasonable default for most desktops and servers.
|
||||
This is a reasonable default for most desktops and servers.
|
||||
"default" is a synonym for "normal".
|
||||
.PP
|
||||
.I powersave
|
||||
.I performance
|
||||
Set a policy for maximum performance,
|
||||
accepting no performance sacrifice for the benefit of energy efficiency.
|
||||
.PP
|
||||
.I balance-performance
|
||||
Set a policy with a high priority on performance,
|
||||
but allowing some performance loss to benefit energy efficiency.
|
||||
.PP
|
||||
.I balance-power
|
||||
Set a policy where the performance and power are balanced.
|
||||
This is the default.
|
||||
.PP
|
||||
.I power
|
||||
Set a policy where the processor can accept
|
||||
a measurable performance hit to maximize energy efficiency.
|
||||
.PP
|
||||
.I n
|
||||
Set MSR_IA32_ENERGY_PERF_BIAS to the specified number.
|
||||
The range of valid numbers is 0-15, where 0 is maximum
|
||||
performance and 15 is maximum energy efficiency.
|
||||
a measurable performance impact to maximize energy efficiency.
|
||||
|
||||
.PP
|
||||
The following table shows the mapping from the value strings above to actual MSR values.
|
||||
This mapping is defined in the Linux-kernel header, msr-index.h.
|
||||
|
||||
.nf
|
||||
VALUE STRING EPB EPP
|
||||
performance 0 0
|
||||
balance-performance 4 128
|
||||
normal, default 6 128
|
||||
balance-power 8 192
|
||||
power 15 255
|
||||
.fi
|
||||
.PP
|
||||
For MSR_IA32_HWP_REQUEST performance fields
|
||||
(--hwp-min, --hwp-max, --hwp-desired), the value option
|
||||
is in units of 100 MHz, Eg. 12 signifies 1200 MHz.
|
||||
|
||||
.SS FIELD OPTIONS
|
||||
\fB-a, --all value-string\fP Sets all EPB and EPP and HWP limit fields to the value associated with
|
||||
the value-string. In addition, enables turbo-mode and HWP-mode, if they were previous disabled.
|
||||
Thus "--all normal" will set a system without cpufreq into a well known configuration.
|
||||
.PP
|
||||
\fB-B, --epb\fP set EPB per-core or per-package.
|
||||
See value strings in the table above.
|
||||
.PP
|
||||
\fB-d, --debug\fP debug increases verbosity. By default
|
||||
x86_energy_perf_policy is silent for updates,
|
||||
and verbose for read-only mode.
|
||||
.PP
|
||||
\fB-P, --hwp-epp\fP set HWP.EPP per-core or per-package.
|
||||
See value strings in the table above.
|
||||
.PP
|
||||
\fB-m, --hwp-min\fP request HWP to not go below the specified core/bus ratio.
|
||||
The "default" is the value found in IA32_HWP_CAPABILITIES.min.
|
||||
.PP
|
||||
\fB-M, --hwp-max\fP request HWP not exceed a the specified core/bus ratio.
|
||||
The "default" is the value found in IA32_HWP_CAPABILITIES.max.
|
||||
.PP
|
||||
\fB-D, --hwp-desired\fP request HWP 'desired' frequency.
|
||||
The "normal" setting is 0, which
|
||||
corresponds to 'full autonomous' HWP control.
|
||||
Non-zero performance values request a specific performance
|
||||
level on this processor, specified in multiples of 100 MHz.
|
||||
.PP
|
||||
\fB-w, --hwp-window\fP specify integer number of microsec
|
||||
in the sliding window that HWP uses to maintain average frequency.
|
||||
This parameter is meaningful only when the "desired" field above is non-zero.
|
||||
Default is 0, allowing the HW to choose.
|
||||
.SH OTHER OPTIONS
|
||||
.PP
|
||||
\fB-f, --force\fP writes the specified values without bounds checking.
|
||||
.PP
|
||||
\fB-U, --hwp-use-pkg\fP (0 | 1), when used in conjunction with --cpu,
|
||||
indicates whether the per-CPU MSR_IA32_HWP_REQUEST should be overruled (1)
|
||||
or exempt (0) from per-Package MSR_IA32_HWP_REQUEST_PKG settings.
|
||||
The default is exempt.
|
||||
.PP
|
||||
\fB-H, --hwp-enable\fP enable HardWare-P-state (HWP) mode. Once enabled, system RESET is required to disable HWP mode.
|
||||
.PP
|
||||
\fB-t, --turbo-enable\fP enable (1) or disable (0) turbo mode.
|
||||
.PP
|
||||
\fB-v, --version\fP print version and exit.
|
||||
.PP
|
||||
If no request to change policy is made,
|
||||
the default behavior is to read
|
||||
and display the current system state,
|
||||
including the default capabilities.
|
||||
.SH WARNING
|
||||
.PP
|
||||
This utility writes directly to Model Specific Registers.
|
||||
There is no locking or coordination should this utility
|
||||
be used to modify HWP limit fields at the same time that
|
||||
intel_pstate's sysfs attributes access the same MSRs.
|
||||
.PP
|
||||
Note that --hwp-desired and --hwp-window are considered experimental.
|
||||
Future versions of Linux reserve the right to access these
|
||||
fields internally -- potentially conflicting with user-space access.
|
||||
.SH EXAMPLE
|
||||
.nf
|
||||
# sudo x86_energy_perf_policy
|
||||
cpu0: EPB 6
|
||||
cpu0: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
|
||||
cpu0: HWP_CAP: low 1 eff 8 guar 27 high 35
|
||||
cpu1: EPB 6
|
||||
cpu1: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
|
||||
cpu1: HWP_CAP: low 1 eff 8 guar 27 high 35
|
||||
cpu2: EPB 6
|
||||
cpu2: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
|
||||
cpu2: HWP_CAP: low 1 eff 8 guar 27 high 35
|
||||
cpu3: EPB 6
|
||||
cpu3: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
|
||||
cpu3: HWP_CAP: low 1 eff 8 guar 27 high 35
|
||||
.fi
|
||||
.SH NOTES
|
||||
.B "x86_energy_perf_policy "
|
||||
.B "x86_energy_perf_policy"
|
||||
runs only as root.
|
||||
.SH FILES
|
||||
.ta
|
||||
.nf
|
||||
/dev/cpu/*/msr
|
||||
.fi
|
||||
|
||||
.SH "SEE ALSO"
|
||||
.nf
|
||||
msr(4)
|
||||
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
|
||||
.fi
|
||||
.PP
|
||||
.SH AUTHORS
|
||||
.nf
|
||||
Written by Len Brown <len.brown@intel.com>
|
||||
Len Brown
|
||||
|
|
|
|||
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