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MIPS: mm: XBurst CPU requires sync after DMA
I am not sure why this is required, but if this is not enabled, reading from a buffer in which data has been DMA'd may read incorrect values. This used to happen for instance in mmc_app_send_scr() (drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied by the CPU to a different location. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -112,6 +112,7 @@ config MACH_INGENIC
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_ZBOOT
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select DMA_NONCOHERENT
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select IRQ_MIPS_CPU
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select PINCTRL
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select GPIOLIB
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@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void)
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case CPU_R12000:
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case CPU_BMIPS5000:
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case CPU_LOONGSON2EF:
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case CPU_XBURST:
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return true;
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default:
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/*
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