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https://github.com/torvalds/linux
synced 2024-09-23 21:07:52 +00:00
drm/i915: Convert the ddi cdclk code to get_display_clock_speed
Unify the HSW/BDW/SKL cdclk extraction code to conform to the same .get_display_clock_speed() mold that all the other platforms use. v2: Update due to SKL code getting added v3: Rebase on top of -nightly (introduction of intel_audio.c) (Mika Kahola) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Add v3 note as suggested by Damien.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -485,7 +485,8 @@ static int i915_audio_component_get_cdclk_freq(struct device *dev)
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return -ENODEV;
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return -ENODEV;
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intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
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intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
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ret = intel_ddi_get_cdclk_freq(dev_priv);
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ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
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intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
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intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
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return ret;
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return ret;
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@ -1689,105 +1689,6 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
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}
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}
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}
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}
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static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
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{
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uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
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uint32_t cdctl = I915_READ(CDCLK_CTL);
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uint32_t linkrate;
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if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
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WARN(1, "LCPLL1 not enabled\n");
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return 24000; /* 24MHz is the cd freq with NSSC ref */
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}
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if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
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return 540000;
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linkrate = (I915_READ(DPLL_CTRL1) &
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DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
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if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
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linkrate == DPLL_CRTL1_LINK_RATE_1080) {
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/* vco 8640 */
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switch (cdctl & CDCLK_FREQ_SEL_MASK) {
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case CDCLK_FREQ_450_432:
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return 432000;
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case CDCLK_FREQ_337_308:
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return 308570;
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case CDCLK_FREQ_675_617:
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return 617140;
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default:
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WARN(1, "Unknown cd freq selection\n");
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}
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} else {
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/* vco 8100 */
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switch (cdctl & CDCLK_FREQ_SEL_MASK) {
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case CDCLK_FREQ_450_432:
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return 450000;
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case CDCLK_FREQ_337_308:
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return 337500;
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case CDCLK_FREQ_675_617:
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return 675000;
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default:
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WARN(1, "Unknown cd freq selection\n");
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}
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}
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/* error case, do as if DPLL0 isn't enabled */
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return 24000;
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}
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static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
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{
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uint32_t lcpll = I915_READ(LCPLL_CTL);
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uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
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if (lcpll & LCPLL_CD_SOURCE_FCLK)
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return 800000;
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else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
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return 450000;
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else if (freq == LCPLL_CLK_FREQ_450)
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return 450000;
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else if (freq == LCPLL_CLK_FREQ_54O_BDW)
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return 540000;
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else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
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return 337500;
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else
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return 675000;
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}
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static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
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{
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struct drm_device *dev = dev_priv->dev;
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uint32_t lcpll = I915_READ(LCPLL_CTL);
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uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
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if (lcpll & LCPLL_CD_SOURCE_FCLK)
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return 800000;
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else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
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return 450000;
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else if (freq == LCPLL_CLK_FREQ_450)
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return 450000;
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else if (IS_HSW_ULT(dev))
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return 337500;
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else
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return 540000;
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}
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int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
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{
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struct drm_device *dev = dev_priv->dev;
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if (IS_SKYLAKE(dev))
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return skl_get_cdclk_freq(dev_priv);
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if (IS_BROADWELL(dev))
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return bdw_get_cdclk_freq(dev_priv);
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/* Haswell */
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return hsw_get_cdclk_freq(dev_priv);
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}
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static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
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static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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struct intel_shared_dpll *pll)
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{
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{
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@ -1974,7 +1875,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
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hsw_shared_dplls_init(dev_priv);
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hsw_shared_dplls_init(dev_priv);
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DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
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DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
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intel_ddi_get_cdclk_freq(dev_priv));
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dev_priv->display.get_display_clock_speed(dev));
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if (IS_SKYLAKE(dev)) {
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if (IS_SKYLAKE(dev)) {
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if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
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if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
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@ -5864,6 +5864,93 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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return 0;
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return 0;
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}
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}
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static int skylake_get_display_clock_speed(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
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uint32_t cdctl = I915_READ(CDCLK_CTL);
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uint32_t linkrate;
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if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
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WARN(1, "LCPLL1 not enabled\n");
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return 24000; /* 24MHz is the cd freq with NSSC ref */
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}
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if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
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return 540000;
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linkrate = (I915_READ(DPLL_CTRL1) &
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DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
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if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
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linkrate == DPLL_CRTL1_LINK_RATE_1080) {
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/* vco 8640 */
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switch (cdctl & CDCLK_FREQ_SEL_MASK) {
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case CDCLK_FREQ_450_432:
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return 432000;
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case CDCLK_FREQ_337_308:
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return 308570;
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case CDCLK_FREQ_675_617:
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return 617140;
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default:
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WARN(1, "Unknown cd freq selection\n");
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}
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} else {
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/* vco 8100 */
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switch (cdctl & CDCLK_FREQ_SEL_MASK) {
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case CDCLK_FREQ_450_432:
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return 450000;
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case CDCLK_FREQ_337_308:
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return 337500;
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case CDCLK_FREQ_675_617:
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return 675000;
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default:
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WARN(1, "Unknown cd freq selection\n");
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}
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}
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/* error case, do as if DPLL0 isn't enabled */
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return 24000;
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}
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static int broadwell_get_display_clock_speed(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t lcpll = I915_READ(LCPLL_CTL);
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uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
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if (lcpll & LCPLL_CD_SOURCE_FCLK)
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return 800000;
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else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
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return 450000;
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else if (freq == LCPLL_CLK_FREQ_450)
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return 450000;
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else if (freq == LCPLL_CLK_FREQ_54O_BDW)
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return 540000;
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else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
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return 337500;
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else
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return 675000;
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}
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static int haswell_get_display_clock_speed(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t lcpll = I915_READ(LCPLL_CTL);
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uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
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if (lcpll & LCPLL_CD_SOURCE_FCLK)
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return 800000;
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else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
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return 450000;
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else if (freq == LCPLL_CLK_FREQ_450)
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return 450000;
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else if (IS_HSW_ULT(dev))
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return 337500;
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else
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return 540000;
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}
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static int valleyview_get_display_clock_speed(struct drm_device *dev)
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static int valleyview_get_display_clock_speed(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -13500,7 +13587,16 @@ static void intel_init_display(struct drm_device *dev)
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}
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}
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/* Returns the core display clock speed */
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/* Returns the core display clock speed */
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if (IS_VALLEYVIEW(dev))
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if (IS_SKYLAKE(dev))
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dev_priv->display.get_display_clock_speed =
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skylake_get_display_clock_speed;
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else if (IS_BROADWELL(dev))
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dev_priv->display.get_display_clock_speed =
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broadwell_get_display_clock_speed;
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else if (IS_HASWELL(dev))
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dev_priv->display.get_display_clock_speed =
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haswell_get_display_clock_speed;
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else if (IS_VALLEYVIEW(dev))
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dev_priv->display.get_display_clock_speed =
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dev_priv->display.get_display_clock_speed =
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valleyview_get_display_clock_speed;
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valleyview_get_display_clock_speed;
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else if (IS_GEN5(dev))
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else if (IS_GEN5(dev))
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@ -717,7 +717,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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if (intel_dig_port->port == PORT_A) {
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if (intel_dig_port->port == PORT_A) {
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if (index)
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if (index)
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return 0;
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return 0;
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return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
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} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
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} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
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/* Workaround for non-ULT HSW */
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/* Workaround for non-ULT HSW */
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switch (index) {
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switch (index) {
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@ -855,7 +855,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc);
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void intel_ddi_init(struct drm_device *dev, enum port port);
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void intel_ddi_init(struct drm_device *dev, enum port port);
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enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
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enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
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bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
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bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
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int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
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void intel_ddi_pll_init(struct drm_device *dev);
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void intel_ddi_pll_init(struct drm_device *dev);
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void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
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void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
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void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
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void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
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@ -1792,7 +1792,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
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linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
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linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
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mode->crtc_clock);
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mode->crtc_clock);
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ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
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ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
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intel_ddi_get_cdclk_freq(dev_priv));
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dev_priv->display.get_display_clock_speed(dev_priv->dev));
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return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
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return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
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PIPE_WM_LINETIME_TIME(linetime);
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PIPE_WM_LINETIME_TIME(linetime);
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