mirror of
https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
MIPS: Replace use of phys_t with phys_addr_t.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
34adb28d50
commit
15d45cce3a
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@ -72,7 +72,7 @@ void __init plat_mem_setup(void)
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
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/* This routine should be valid for all Au1x based boards */
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phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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unsigned long start = ALCHEMY_PCI_MEMWIN_START;
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unsigned long end = ALCHEMY_PCI_MEMWIN_END;
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@ -83,7 +83,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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/* Check for PCI memory window */
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if (phys_addr >= start && (phys_addr + size - 1) <= end)
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return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
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return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
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/* default nop */
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return phys_addr;
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@ -262,8 +262,8 @@ char *octeon_swiotlb;
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void __init plat_swiotlb_setup(void)
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{
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int i;
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phys_t max_addr;
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phys_t addr_size;
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phys_addr_t max_addr;
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phys_addr_t addr_size;
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size_t swiotlbsize;
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unsigned long swiotlb_nslabs;
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@ -98,16 +98,16 @@ extern unsigned long mips_machtype;
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struct boot_mem_map {
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int nr_map;
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struct boot_mem_map_entry {
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phys_t addr; /* start of memory segment */
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phys_t size; /* size of memory segment */
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phys_addr_t addr; /* start of memory segment */
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phys_addr_t size; /* size of memory segment */
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long type; /* type of memory segment */
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} map[BOOT_MEM_MAP_MAX];
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};
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extern struct boot_mem_map boot_mem_map;
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extern void add_memory_region(phys_t start, phys_t size, long type);
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extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max);
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extern void add_memory_region(phys_addr_t start, phys_addr_t size, long type);
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extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
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extern void prom_init(void);
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extern void prom_free_prom_memory(void);
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@ -167,7 +167,7 @@ static inline void * isa_bus_to_virt(unsigned long address)
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*/
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#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
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extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
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extern void __iounmap(const volatile void __iomem *addr);
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#ifndef CONFIG_PCI
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@ -175,7 +175,7 @@ struct pci_dev;
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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#endif
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static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
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static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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void __iomem *addr = plat_ioremap(offset, size, flags);
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@ -183,7 +183,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
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if (addr)
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return addr;
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#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
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#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
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if (cpu_has_64bit_addresses) {
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u64 base = UNCAC_BASE;
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@ -197,7 +197,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
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return (void __iomem *) (unsigned long) (base + offset);
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} else if (__builtin_constant_p(offset) &&
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__builtin_constant_p(size) && __builtin_constant_p(flags)) {
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phys_t phys_addr, last_addr;
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phys_addr_t phys_addr, last_addr;
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phys_addr = fixup_bigphys_addr(offset, size);
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@ -12,9 +12,9 @@
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#include <linux/types.h>
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
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extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
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extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
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#else
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static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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@ -23,12 +23,12 @@ static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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/*
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* Allow physical addresses to be fixed up to help 36-bit peripherals.
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*/
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static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return __fixup_bigphys_addr(phys_addr, size);
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}
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static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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return NULL;
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@ -3,12 +3,12 @@
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#include <bcm63xx_cpu.h>
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static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline int is_bcm63xx_internal_registers(phys_t offset)
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static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
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{
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switch (bcm63xx_get_cpu_id()) {
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case BCM3368_CPU_ID:
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@ -32,7 +32,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
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return 0;
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}
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static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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if (is_bcm63xx_internal_registers(offset))
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@ -15,12 +15,12 @@
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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return NULL;
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@ -15,12 +15,12 @@
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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#define TXX9_DIRECTMAP_BASE 0xff000000ul
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@ -15,12 +15,12 @@
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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#ifdef CONFIG_64BIT
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@ -30,7 +30,7 @@ extern void __iomem *mips_cm_l2sync_base;
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* different way by defining a function with the same prototype except for the
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* name mips_cm_phys_base (without underscores).
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*/
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extern phys_t __mips_cm_phys_base(void);
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extern phys_addr_t __mips_cm_phys_base(void);
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/**
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* mips_cm_probe - probe for a Coherence Manager
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@ -25,7 +25,7 @@ extern void __iomem *mips_cpc_base;
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* memory mapped registers. This is platform dependant & must therefore be
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* implemented per-platform.
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*/
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extern phys_t mips_cpc_default_phys_base(void);
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extern phys_addr_t mips_cpc_default_phys_base(void);
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/**
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* mips_cpc_phys_base - retrieve the physical base address of the CPC
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* is present. It may be overriden by individual platforms which determine
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* this address in a different way.
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*/
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extern phys_t __weak mips_cpc_phys_base(void);
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extern phys_addr_t __weak mips_cpc_phys_base(void);
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/**
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* mips_cpc_probe - probe for a Cluster Power Controller
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@ -84,7 +84,7 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc, resource_size_t *start,
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resource_size_t *end)
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{
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phys_t size = resource_size(rsrc);
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phys_addr_t size = resource_size(rsrc);
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*start = fixup_bigphys_addr(rsrc->start, size);
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*end = rsrc->start + size;
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@ -428,7 +428,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
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unsigned long size,
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pgprot_t prot)
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{
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phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
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phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
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return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
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}
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#define io_remap_pfn_range io_remap_pfn_range
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@ -20,12 +20,12 @@
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#ifndef __ASSEMBLY__
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/*
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* Don't use phys_t. You've been warned.
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* Don't use phys_addr_t. You've been warned.
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*/
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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typedef unsigned long long phys_t;
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typedef unsigned long long phys_addr_t;
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#else
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typedef unsigned long phys_t;
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typedef unsigned long phys_addr_t;
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#endif
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#endif /* __ASSEMBLY__ */
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@ -32,7 +32,7 @@ static void __init jz4740_detect_mem(void)
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{
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void __iomem *jz_emc_base;
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u32 ctrl, bus, bank, rows, cols;
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phys_t size;
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phys_addr_t size;
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jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
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ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
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@ -16,7 +16,7 @@
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void __iomem *mips_cm_base;
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void __iomem *mips_cm_l2sync_base;
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phys_t __mips_cm_phys_base(void)
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phys_addr_t __mips_cm_phys_base(void)
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{
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u32 config3 = read_c0_config3();
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u32 cmgcr;
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return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
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}
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phys_t mips_cm_phys_base(void)
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phys_addr_t mips_cm_phys_base(void)
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__attribute__((weak, alias("__mips_cm_phys_base")));
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phys_t __mips_cm_l2sync_phys_base(void)
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phys_addr_t __mips_cm_l2sync_phys_base(void)
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{
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u32 base_reg;
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return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
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}
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phys_t mips_cm_l2sync_phys_base(void)
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phys_addr_t mips_cm_l2sync_phys_base(void)
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__attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
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static void mips_cm_probe_l2sync(void)
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{
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unsigned major_rev;
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phys_t addr;
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phys_addr_t addr;
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/* L2-only sync was introduced with CM major revision 6 */
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major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
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int mips_cm_probe(void)
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{
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phys_t addr;
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phys_addr_t addr;
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u32 base_reg;
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addr = mips_cm_phys_base();
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@ -21,7 +21,7 @@ static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
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static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
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phys_t __weak mips_cpc_phys_base(void)
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phys_addr_t __weak mips_cpc_phys_base(void)
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{
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u32 cpc_base;
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int mips_cpc_probe(void)
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{
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phys_t addr;
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phys_addr_t addr;
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unsigned cpu;
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for_each_possible_cpu(cpu)
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@ -82,7 +82,7 @@ static struct resource data_resource = { .name = "Kernel data", };
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static void *detect_magic __initdata = detect_memory_region;
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void __init add_memory_region(phys_t start, phys_t size, long type)
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void __init add_memory_region(phys_addr_t start, phys_addr_t size, long type)
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{
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int x = boot_mem_map.nr_map;
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int i;
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boot_mem_map.nr_map++;
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}
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void __init detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max)
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void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max)
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{
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void *dm = &detect_magic;
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phys_t size;
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phys_addr_t size;
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for (size = sz_min; size < sz_max; size <<= 1) {
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if (!memcmp(dm, dm + size, sizeof(detect_magic)))
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early_param("elfcorehdr", early_parse_elfcorehdr);
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#endif
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static void __init arch_mem_addpart(phys_t mem, phys_t end, int type)
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static void __init arch_mem_addpart(phys_addr_t mem, phys_addr_t end, int type)
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{
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phys_t size;
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phys_addr_t size;
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int i;
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size = end - mem;
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@ -17,9 +17,9 @@
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#include <asm/tlbflush.h>
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static inline void remap_area_pte(pte_t * pte, unsigned long address,
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phys_t size, phys_t phys_addr, unsigned long flags)
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phys_addr_t size, phys_addr_t phys_addr, unsigned long flags)
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{
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phys_t end;
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phys_addr_t end;
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unsigned long pfn;
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pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE
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| __WRITEABLE | flags);
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}
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static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
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phys_t size, phys_t phys_addr, unsigned long flags)
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phys_addr_t size, phys_addr_t phys_addr, unsigned long flags)
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{
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phys_t end;
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phys_addr_t end;
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address &= ~PGDIR_MASK;
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end = address + size;
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@ -64,8 +64,8 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
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return 0;
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}
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static int remap_area_pages(unsigned long address, phys_t phys_addr,
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phys_t size, unsigned long flags)
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static int remap_area_pages(unsigned long address, phys_addr_t phys_addr,
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phys_addr_t size, unsigned long flags)
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{
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int error;
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pgd_t * dir;
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@ -111,13 +111,13 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
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* caller shouldn't need to know that small detail.
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*/
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#define IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
|
||||
#define IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
|
||||
|
||||
void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
|
||||
void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long flags)
|
||||
{
|
||||
struct vm_struct * area;
|
||||
unsigned long offset;
|
||||
phys_t last_addr;
|
||||
phys_addr_t last_addr;
|
||||
void * addr;
|
||||
|
||||
phys_addr = fixup_bigphys_addr(phys_addr, size);
|
||||
|
|
|
@ -111,7 +111,7 @@ static void __init mips_ejtag_setup(void)
|
|||
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
|
||||
}
|
||||
|
||||
phys_t mips_cpc_default_phys_base(void)
|
||||
phys_addr_t mips_cpc_default_phys_base(void)
|
||||
{
|
||||
return CPC_BASE_ADDR;
|
||||
}
|
||||
|
|
|
@ -122,8 +122,8 @@ void __init prom_setup_cmdline(void)
|
|||
void __init prom_init(void)
|
||||
{
|
||||
struct ddr_ram __iomem *ddr;
|
||||
phys_t memsize;
|
||||
phys_t ddrbase;
|
||||
phys_addr_t memsize;
|
||||
phys_addr_t ddrbase;
|
||||
|
||||
ddr = ioremap_nocache(ddr_reg[0].start,
|
||||
ddr_reg[0].end - ddr_reg[0].start);
|
||||
|
@ -133,8 +133,8 @@ void __init prom_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
ddrbase = (phys_t)&ddr->ddrbase;
|
||||
memsize = (phys_t)&ddr->ddrmask;
|
||||
ddrbase = (phys_addr_t)&ddr->ddrbase;
|
||||
memsize = (phys_addr_t)&ddr->ddrmask;
|
||||
memsize = 0 - memsize;
|
||||
|
||||
prom_setup_cmdline();
|
||||
|
|
|
@ -49,8 +49,8 @@
|
|||
#endif
|
||||
|
||||
#define SIBYTE_MAX_MEM_REGIONS 8
|
||||
phys_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
|
||||
phys_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
|
||||
phys_addr_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
|
||||
phys_addr_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
|
||||
unsigned int board_mem_region_count;
|
||||
|
||||
int cfe_cons_handle;
|
||||
|
|
|
@ -50,7 +50,7 @@ static struct platform_device swarm_pata_device = {
|
|||
static int __init swarm_pata_init(void)
|
||||
{
|
||||
u8 __iomem *base;
|
||||
phys_t offset, size;
|
||||
phys_addr_t offset, size;
|
||||
struct resource *r;
|
||||
|
||||
if (!SIBYTE_HAVE_IDE)
|
||||
|
|
Loading…
Reference in a new issue