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https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
MIPS: refactor the runtime coherent vs noncoherent DMA indicators
Replace the global coherentio enum, and the hw_coherentio (fake) boolean variables with a single boolean dma_default_coherent flag. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -65,8 +65,7 @@ void __init plat_mem_setup(void)
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/* Clear to obtain best system bus performance */
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clear_c0_config(1 << 19); /* Clear Config[OD] */
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coherentio = alchemy_dma_coherent() ?
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IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;
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dma_default_coherent = alchemy_dma_coherent();
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board_setup(); /* board specific setup */
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@ -9,30 +9,14 @@
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#ifndef __ASM_DMA_COHERENCE_H
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#define __ASM_DMA_COHERENCE_H
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enum coherent_io_user_state {
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IO_COHERENCE_DEFAULT,
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IO_COHERENCE_ENABLED,
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IO_COHERENCE_DISABLED,
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};
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#if defined(CONFIG_DMA_PERDEV_COHERENT)
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/* Don't provide (hw_)coherentio to avoid misuse */
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#elif defined(CONFIG_DMA_MAYBE_COHERENT)
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extern enum coherent_io_user_state coherentio;
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extern int hw_coherentio;
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#ifdef CONFIG_DMA_MAYBE_COHERENT
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extern bool dma_default_coherent;
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static inline bool dev_is_dma_coherent(struct device *dev)
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{
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return coherentio == IO_COHERENCE_ENABLED ||
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(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
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return dma_default_coherent;
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}
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#else
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#ifdef CONFIG_DMA_NONCOHERENT
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#define coherentio IO_COHERENCE_DISABLED
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#else
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#define coherentio IO_COHERENCE_ENABLED
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#define dma_default_coherent (!IS_ENABLED(CONFIG_DMA_NONCOHERENT))
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#endif
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#define hw_coherentio 0
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#endif /* CONFIG_DMA_MAYBE_COHERENT */
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#endif
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@ -803,14 +803,12 @@ arch_initcall(debugfs_mips);
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#endif
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#ifdef CONFIG_DMA_MAYBE_COHERENT
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/* User defined DMA coherency from command line. */
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enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
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EXPORT_SYMBOL_GPL(coherentio);
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int hw_coherentio; /* Actual hardware supported DMA coherency setting. */
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bool dma_default_coherent;
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EXPORT_SYMBOL_GPL(dma_default_coherent);
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static int __init setcoherentio(char *str)
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{
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coherentio = IO_COHERENCE_ENABLED;
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dma_default_coherent = true;
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pr_info("Hardware DMA cache coherency (command line)\n");
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return 0;
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}
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@ -818,7 +816,7 @@ early_param("coherentio", setcoherentio);
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static int __init setnocoherentio(char *str)
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{
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coherentio = IO_COHERENCE_DISABLED;
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dma_default_coherent = true;
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pr_info("Software DMA cache coherency (command line)\n");
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return 0;
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}
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@ -1914,15 +1914,11 @@ void r4k_cache_init(void)
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__local_flush_icache_user_range = local_r4k_flush_icache_user_range;
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#ifdef CONFIG_DMA_NONCOHERENT
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#ifdef CONFIG_DMA_MAYBE_COHERENT
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if (coherentio == IO_COHERENCE_ENABLED ||
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(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
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if (dma_default_coherent) {
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_dma_cache_wback_inv = (void *)cache_noop;
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_dma_cache_wback = (void *)cache_noop;
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_dma_cache_inv = (void *)cache_noop;
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} else
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#endif /* CONFIG_DMA_MAYBE_COHERENT */
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{
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} else {
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_dma_cache_wback_inv = r4k_dma_cache_wback_inv;
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_dma_cache_wback = r4k_dma_cache_wback_inv;
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_dma_cache_inv = r4k_dma_cache_inv;
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@ -98,7 +98,7 @@ static void __init plat_setup_iocoherency(void)
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if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
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pr_info("Enabled Bonito CPU coherency\n");
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hw_coherentio = 1;
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dma_default_coherent = true;
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}
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if (strstr(fw_getcmdline(), "iobcuncached")) {
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BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
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@ -118,12 +118,12 @@ static void __init plat_setup_iocoherency(void)
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pr_info("CMP IOCU detected\n");
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cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
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if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
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hw_coherentio = 1;
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dma_default_coherent = true;
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else
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pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
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}
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if (hw_coherentio)
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if (dma_default_coherent)
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pr_info("Hardware DMA cache coherency enabled\n");
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else
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pr_info("Software DMA cache coherency enabled\n");
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@ -429,9 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev)
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ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
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/* Au1500 revisions older than AD have borked coherent PCI */
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if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
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(read_c0_prid() < 0x01030202) &&
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(coherentio == IO_COHERENCE_DISABLED)) {
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if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 &&
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read_c0_prid() < 0x01030202 && !dma_default_coherent) {
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val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
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val |= PCI_CONFIG_NC;
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__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
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