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clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Claudiu Beznea
Stephen Boyd
parent
f803858af8
commit
120d5d8b46
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@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_layout_divio = {
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.endiv_shift = 30,
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};
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/*
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* CPU PLL output range.
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* Notice: The upper limit has been setup to 1000000002 due to hardware
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* block which cannot output exactly 1GHz.
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*/
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static const struct clk_range cpu_pll_outputs[] = {
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{ .min = 2343750, .max = 1000000002 },
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};
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/* PLL output range. */
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static const struct clk_range pll_outputs[] = {
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{ .min = 2343750, .max = 1200000000 },
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};
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/* CPU PLL characteristics. */
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static const struct clk_pll_characteristics cpu_pll_characteristics = {
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.input = { .min = 12000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(cpu_pll_outputs),
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.output = cpu_pll_outputs,
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};
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/* PLL characteristics. */
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static const struct clk_pll_characteristics pll_characteristics = {
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.input = { .min = 12000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(pll_outputs),
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.output = pll_outputs,
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};
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/**
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* PLL clocks description
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* @n: clock name
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* @p: clock parent
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* @l: clock layout
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* @c: clock characteristics
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* @t: clock type
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* @f: clock flags
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* @eid: export index in sama7g5->chws[] array
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@ -102,6 +131,7 @@ static const struct {
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const char *n;
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const char *p;
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const struct clk_pll_layout *l;
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const struct clk_pll_characteristics *c;
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unsigned long f;
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u8 t;
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u8 eid;
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@ -110,6 +140,7 @@ static const struct {
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{ .n = "cpupll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.c = &cpu_pll_characteristics,
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.t = PLL_TYPE_FRAC,
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/*
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* This feeds cpupll_divpmcck which feeds CPU. It should
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@ -120,6 +151,7 @@ static const struct {
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{ .n = "cpupll_divpmcck",
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.p = "cpupll_fracck",
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.l = &pll_layout_divpmc,
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.c = &cpu_pll_characteristics,
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.t = PLL_TYPE_DIV,
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/* This feeds CPU. It should not be disabled. */
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.f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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@ -130,6 +162,7 @@ static const struct {
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{ .n = "syspll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.c = &pll_characteristics,
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.t = PLL_TYPE_FRAC,
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/*
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* This feeds syspll_divpmcck which may feed critial parts
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@ -141,6 +174,7 @@ static const struct {
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{ .n = "syspll_divpmcck",
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.p = "syspll_fracck",
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.l = &pll_layout_divpmc,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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/*
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* This may feed critial parts of the systems like timers.
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@ -154,6 +188,7 @@ static const struct {
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{ .n = "ddrpll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.c = &pll_characteristics,
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.t = PLL_TYPE_FRAC,
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/*
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* This feeds ddrpll_divpmcck which feeds DDR. It should not
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@ -164,6 +199,7 @@ static const struct {
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{ .n = "ddrpll_divpmcck",
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.p = "ddrpll_fracck",
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.l = &pll_layout_divpmc,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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/* This feeds DDR. It should not be disabled. */
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.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
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@ -173,12 +209,14 @@ static const struct {
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{ .n = "imgpll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.c = &pll_characteristics,
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.t = PLL_TYPE_FRAC,
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.f = CLK_SET_RATE_GATE, },
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{ .n = "imgpll_divpmcck",
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.p = "imgpll_fracck",
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.l = &pll_layout_divpmc,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT, },
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@ -188,12 +226,14 @@ static const struct {
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{ .n = "baudpll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.c = &pll_characteristics,
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.t = PLL_TYPE_FRAC,
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.f = CLK_SET_RATE_GATE, },
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{ .n = "baudpll_divpmcck",
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.p = "baudpll_fracck",
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.l = &pll_layout_divpmc,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT, },
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@ -203,12 +243,14 @@ static const struct {
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{ .n = "audiopll_fracck",
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.p = "main_xtal",
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.l = &pll_layout_frac,
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.c = &pll_characteristics,
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.t = PLL_TYPE_FRAC,
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.f = CLK_SET_RATE_GATE, },
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{ .n = "audiopll_divpmcck",
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.p = "audiopll_fracck",
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.l = &pll_layout_divpmc,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT,
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@ -217,6 +259,7 @@ static const struct {
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{ .n = "audiopll_diviock",
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.p = "audiopll_fracck",
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.l = &pll_layout_divio,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT,
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@ -227,12 +270,14 @@ static const struct {
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{ .n = "ethpll_fracck",
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.p = "main_xtal",
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.l = &pll_layout_frac,
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.c = &pll_characteristics,
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.t = PLL_TYPE_FRAC,
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.f = CLK_SET_RATE_GATE, },
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{ .n = "ethpll_divpmcck",
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.p = "ethpll_fracck",
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.l = &pll_layout_divpmc,
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.c = &pll_characteristics,
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.t = PLL_TYPE_DIV,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT, },
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@ -793,18 +838,6 @@ static const struct {
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.pp_chg_id = INT_MIN, },
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};
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/* PLL output range. */
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static const struct clk_range pll_outputs[] = {
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{ .min = 2343750, .max = 1200000000 },
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};
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/* PLL characteristics. */
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static const struct clk_pll_characteristics pll_characteristics = {
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.input = { .min = 12000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(pll_outputs),
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.output = pll_outputs,
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};
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/* MCK0 characteristics. */
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static const struct clk_master_characteristics mck0_characteristics = {
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.output = { .min = 50000000, .max = 200000000 },
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@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
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hw = sam9x60_clk_register_frac_pll(regmap,
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&pmc_pll_lock, sama7g5_plls[i][j].n,
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sama7g5_plls[i][j].p, parent_hw, i,
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&pll_characteristics,
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sama7g5_plls[i][j].c,
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sama7g5_plls[i][j].l,
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sama7g5_plls[i][j].f);
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break;
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@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
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hw = sam9x60_clk_register_div_pll(regmap,
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&pmc_pll_lock, sama7g5_plls[i][j].n,
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sama7g5_plls[i][j].p, i,
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&pll_characteristics,
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sama7g5_plls[i][j].c,
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sama7g5_plls[i][j].l,
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sama7g5_plls[i][j].f);
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break;
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