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pinctrl: tegra: Renumber the GG.0 and GG.1 pins

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There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Thierry Reding 2020-03-19 13:27:36 +01:00 committed by Linus Walleij
parent f67499f8ea
commit 103afc8e9e
1 changed files with 4 additions and 7 deletions
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11
drivers/pinctrl/tegra/pinctrl-tegra194.c
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@ -24,17 +24,14 @@
/* Define unique ID for each pins */
enum pin_id {
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
TEGRA_PIN_NUM_GPIOS = 258,
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
TEGRA_PIN_PEX_L5_RST_N_PGG1,
};
/* Table for pin descriptor */
static const struct pinctrl_pin_desc tegra194_pins[] = {
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
"TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
"TEGRA_PIN_PEX_L5_RST_N_PGG1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
};
static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {