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net: dsa: mv88e6xxx: prefix Global Monitor Control macros
Prefix and document the Global Monitor Control Register macros (which became the Global Monitor & MGMT Control Register with 88E6390) and give a clear 16-bit registers representation. Use __bf_shf to get the shift value at compile time instead of adding new defined macros for it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot
David S. Miller
parent
d77f4321fa
commit
101515c8c5
2 changed files with 60 additions and 43 deletions
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@ -12,6 +12,8 @@
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* (at your option) any later version.
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*/
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#include <linux/bitfield.h>
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#include "chip.h"
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#include "global1.h"
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@ -247,17 +249,17 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_MONITOR_CONTROL, ®);
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err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
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if (err)
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return err;
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reg &= ~(GLOBAL_MONITOR_CONTROL_INGRESS_MASK |
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GLOBAL_MONITOR_CONTROL_EGRESS_MASK);
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reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
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MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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reg |= port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
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port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT;
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reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
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port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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/* Older generations also call this the ARP destination. It has been
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@ -269,14 +271,14 @@ int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_MONITOR_CONTROL, ®);
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err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
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if (err)
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return err;
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reg &= ~GLOBAL_MONITOR_CONTROL_ARP_MASK;
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reg |= port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
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reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
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reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
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return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
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@ -284,55 +286,66 @@ static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
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{
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u16 reg;
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reg = GLOBAL_MONITOR_CONTROL_UPDATE | pointer | data;
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reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
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return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
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return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
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}
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int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 ptr;
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int err;
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err = mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_INGRESS,
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port);
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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return mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_EGRESS,
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port);
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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return 0;
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}
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int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
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{
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return mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_CPU_DEST,
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port);
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u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
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return mv88e6390_g1_monitor_write(chip, ptr, port);
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}
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int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
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{
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u16 ptr;
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int err;
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/* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
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err = mv88e6390_g1_monitor_write(
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chip, GLOBAL_MONITOR_CONTROL_0180C280000000XLO, 0xff);
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
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err = mv88e6390_g1_monitor_write(
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chip, GLOBAL_MONITOR_CONTROL_0180C280000000XHI, 0xff);
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
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err = mv88e6390_g1_monitor_write(
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chip, GLOBAL_MONITOR_CONTROL_0180C280000002XLO, 0xff);
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
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return mv88e6390_g1_monitor_write(
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chip, GLOBAL_MONITOR_CONTROL_0180C280000002XHI, 0xff);
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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return 0;
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}
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/* Offset 0x1c: Global Control 2 */
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@ -156,23 +156,27 @@
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#define GLOBAL_IP_PRI_7 0x17
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#define GLOBAL_IEEE_PRI 0x18
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#define GLOBAL_CORE_TAG_TYPE 0x19
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#define GLOBAL_MONITOR_CONTROL 0x1a
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#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
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#define GLOBAL_MONITOR_CONTROL_INGRESS_MASK (0xf << 12)
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#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
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#define GLOBAL_MONITOR_CONTROL_EGRESS_MASK (0xf << 8)
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#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
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#define GLOBAL_MONITOR_CONTROL_ARP_MASK (0xf << 4)
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#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
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#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
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#define GLOBAL_MONITOR_CONTROL_UPDATE BIT(15)
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#define GLOBAL_MONITOR_CONTROL_0180C280000000XLO (0x00 << 8)
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#define GLOBAL_MONITOR_CONTROL_0180C280000000XHI (0x01 << 8)
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#define GLOBAL_MONITOR_CONTROL_0180C280000002XLO (0x02 << 8)
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#define GLOBAL_MONITOR_CONTROL_0180C280000002XHI (0x03 << 8)
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#define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8)
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#define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8)
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#define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8)
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/* Offset 0x1A: Monitor Control */
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#define MV88E6185_G1_MONITOR_CTL 0x1a
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#define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
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#define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
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#define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
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#define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
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#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
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/* Offset 0x1A: Monitor & MGMT Control Register */
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#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
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#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO 0x0000
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI 0x0100
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO 0x0200
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI 0x0300
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
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#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
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#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
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/* Offset 0x1C: Global Control 2 */
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#define MV88E6XXX_G1_CTL2 0x1c
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