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[MIPS] SMTC: Interrupt mask backstop hack
To support multiple TC microthreads acting as "CPUs" within a VPE, VPE-wide interrupt mask bits must be specially manipulated during interrupt handling. To support legacy drivers and interrupt controller management code, SMTC has a "backstop" to track and if necessary restore the interrupt mask. This has some performance impact on interrupt service overhead. Disable it only if you know what you are doing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1404,6 +1404,19 @@ config MIPS_MT_SMTC_INSTANT_REPLAY
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it off), but ensures that IPIs are handled promptly even under
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it off), but ensures that IPIs are handled promptly even under
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heavy I/O interrupt load.
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heavy I/O interrupt load.
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config MIPS_MT_SMTC_IM_BACKSTOP
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bool "Use per-TC register bits as backstop for inhibited IM bits"
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depends on MIPS_MT_SMTC
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default y
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help
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To support multiple TC microthreads acting as "CPUs" within
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a VPE, VPE-wide interrupt mask bits must be specially manipulated
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during interrupt handling. To support legacy drivers and interrupt
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controller management code, SMTC has a "backstop" to track and
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if necessary restore the interrupt mask. This has some performance
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impact on interrupt service overhead. Disable it only if you know
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what you are doing.
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config MIPS_VPE_LOADER_TOM
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config MIPS_VPE_LOADER_TOM
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bool "Load VPE program into memory hidden from linux"
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bool "Load VPE program into memory hidden from linux"
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depends on MIPS_VPE_LOADER
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depends on MIPS_VPE_LOADER
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@ -84,6 +84,7 @@ FEXPORT(restore_all) # restore full frame
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LONG_S sp, TI_REGS($28)
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LONG_S sp, TI_REGS($28)
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jal deferred_smtc_ipi
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jal deferred_smtc_ipi
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LONG_S s0, TI_REGS($28)
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LONG_S s0, TI_REGS($28)
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#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
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/* Re-arm any temporarily masked interrupts not explicitly "acked" */
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/* Re-arm any temporarily masked interrupts not explicitly "acked" */
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mfc0 v0, CP0_TCSTATUS
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mfc0 v0, CP0_TCSTATUS
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ori v1, v0, TCSTATUS_IXMT
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ori v1, v0, TCSTATUS_IXMT
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@ -110,6 +111,7 @@ FEXPORT(restore_all) # restore full frame
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_ehb
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_ehb
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xor t0, t0, t3
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xor t0, t0, t3
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mtc0 t0, CP0_TCCONTEXT
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mtc0 t0, CP0_TCCONTEXT
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#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
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#endif /* CONFIG_MIPS_MT_SMTC */
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#endif /* CONFIG_MIPS_MT_SMTC */
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.set noat
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.set noat
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RESTORE_TEMP
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RESTORE_TEMP
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@ -243,9 +243,11 @@ NESTED(except_vec_vi_handler, 0, sp)
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*/
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*/
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mfc0 t1, CP0_STATUS
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mfc0 t1, CP0_STATUS
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and t0, a0, t1
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and t0, a0, t1
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#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
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mfc0 t2, CP0_TCCONTEXT
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mfc0 t2, CP0_TCCONTEXT
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or t0, t0, t2
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or t0, t0, t2
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mtc0 t0, CP0_TCCONTEXT
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mtc0 t0, CP0_TCCONTEXT
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#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
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xor t1, t1, t0
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xor t1, t1, t0
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mtc0 t1, CP0_STATUS
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mtc0 t1, CP0_STATUS
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_ehb
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_ehb
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@ -24,7 +24,7 @@ static inline int irq_canonicalize(int irq)
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#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
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#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
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#endif
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
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/*
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/*
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* Clear interrupt mask handling "backstop" if irq_hwmask
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* Clear interrupt mask handling "backstop" if irq_hwmask
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* entry so indicates. This implies that the ack() or end()
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* entry so indicates. This implies that the ack() or end()
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