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crypto: qat - configure arbiter mapping based on engines enabled
The hardware specific function adf_get_arbiter_mapping() modifies the static array thrd_to_arb_map to disable mappings for AEs that are disabled. This static array is used for each device of the same type. If the ae mask is not identical for all devices of the same type then the arbiter mapping returned by adf_get_arbiter_mapping() may be wrong. This patch fixes this problem by ensuring the static arbiter mapping is unchanged and the device arbiter mapping is re-calculated each time based on the static mapping. Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -19,7 +19,7 @@ static struct adf_fw_config adf_4xxx_fw_config[] = {
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};
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/* Worker thread to service arbiter mappings */
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static u32 thrd_to_arb_map[] = {
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static const u32 thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
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0x5555555, 0x5555555, 0x5555555, 0x5555555,
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0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
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0x0
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@ -119,17 +119,9 @@ static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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return DEV_SKU_1;
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}
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static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
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u32 const **arb_map_config)
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static const u32 *adf_get_arbiter_mapping(void)
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{
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struct adf_hw_device_data *hw_device = accel_dev->hw_device;
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unsigned long ae_mask = hw_device->ae_mask;
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int i;
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for_each_clear_bit(i, &ae_mask, ADF_4XXX_MAX_ACCELENGINES)
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thrd_to_arb_map[i] = 0;
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*arb_map_config = thrd_to_arb_map;
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return thrd_to_arb_map;
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}
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static void get_arb_info(struct arb_info *arb_info)
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@ -7,8 +7,8 @@
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#include "adf_c3xxx_hw_data.h"
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#include "icp_qat_hw.h"
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/* Worker thread to service arbiter mappings based on dev SKUs */
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static const u32 thrd_to_arb_map_6_me_sku[] = {
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/* Worker thread to service arbiter mappings */
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static const u32 thrd_to_arb_map[ADF_C3XXX_MAX_ACCELENGINES] = {
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0x12222AAA, 0x11222AAA, 0x12222AAA,
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0x11222AAA, 0x12222AAA, 0x11222AAA
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};
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@ -101,18 +101,9 @@ static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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return DEV_SKU_UNKNOWN;
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}
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static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
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u32 const **arb_map_config)
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static const u32 *adf_get_arbiter_mapping(void)
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{
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switch (accel_dev->accel_pci_dev.sku) {
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case DEV_SKU_4:
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*arb_map_config = thrd_to_arb_map_6_me_sku;
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break;
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default:
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dev_err(&GET_DEV(accel_dev),
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"The configuration doesn't match any SKU");
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*arb_map_config = NULL;
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}
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return thrd_to_arb_map;
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}
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static u32 get_pf2vf_offset(u32 i)
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@ -7,13 +7,8 @@
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#include "adf_c62x_hw_data.h"
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#include "icp_qat_hw.h"
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/* Worker thread to service arbiter mappings based on dev SKUs */
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static const u32 thrd_to_arb_map_8_me_sku[] = {
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0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
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0x11222AAA, 0x12222AAA, 0x11222AAA, 0, 0
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};
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static const u32 thrd_to_arb_map_10_me_sku[] = {
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/* Worker thread to service arbiter mappings */
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static const u32 thrd_to_arb_map[ADF_C62X_MAX_ACCELENGINES] = {
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0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
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0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
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};
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@ -108,21 +103,9 @@ static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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return DEV_SKU_UNKNOWN;
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}
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static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
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u32 const **arb_map_config)
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static const u32 *adf_get_arbiter_mapping(void)
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{
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switch (accel_dev->accel_pci_dev.sku) {
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case DEV_SKU_2:
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*arb_map_config = thrd_to_arb_map_8_me_sku;
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break;
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case DEV_SKU_4:
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*arb_map_config = thrd_to_arb_map_10_me_sku;
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break;
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default:
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dev_err(&GET_DEV(accel_dev),
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"The configuration doesn't match any SKU");
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*arb_map_config = NULL;
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}
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return thrd_to_arb_map;
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}
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static u32 get_pf2vf_offset(u32 i)
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@ -168,8 +168,7 @@ struct adf_hw_device_data {
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int (*send_admin_init)(struct adf_accel_dev *accel_dev);
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int (*init_arb)(struct adf_accel_dev *accel_dev);
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void (*exit_arb)(struct adf_accel_dev *accel_dev);
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void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
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const u32 **cfg);
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const u32 *(*get_arb_mapping)(void);
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void (*disable_iov)(struct adf_accel_dev *accel_dev);
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void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
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bool enable);
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@ -19,6 +19,7 @@ int adf_init_arb(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
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unsigned long ae_mask = hw_data->ae_mask;
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u32 arb_off, wt_off, arb_cfg;
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const u32 *thd_2_arb_cfg;
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struct arb_info info;
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@ -35,12 +36,9 @@ int adf_init_arb(struct adf_accel_dev *accel_dev)
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WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg);
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/* Map worker threads to service arbiters */
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hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg);
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thd_2_arb_cfg = hw_data->get_arb_mapping();
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if (!thd_2_arb_cfg)
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return -EFAULT;
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for (i = 0; i < hw_data->num_engines; i++)
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for_each_set_bit(i, &ae_mask, hw_data->num_engines)
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WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]);
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return 0;
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@ -7,14 +7,8 @@
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#include "adf_dh895xcc_hw_data.h"
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#include "icp_qat_hw.h"
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/* Worker thread to service arbiter mappings based on dev SKUs */
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static const u32 thrd_to_arb_map_sku4[] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x00000000, 0x00000000, 0x00000000, 0x00000000
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};
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static const u32 thrd_to_arb_map_sku6[] = {
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/* Worker thread to service arbiter mappings */
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static const u32 thrd_to_arb_map[ADF_DH895XCC_MAX_ACCELENGINES] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
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@ -127,23 +121,9 @@ static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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return DEV_SKU_UNKNOWN;
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}
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static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
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u32 const **arb_map_config)
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static const u32 *adf_get_arbiter_mapping(void)
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{
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switch (accel_dev->accel_pci_dev.sku) {
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case DEV_SKU_1:
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*arb_map_config = thrd_to_arb_map_sku4;
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break;
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case DEV_SKU_2:
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case DEV_SKU_4:
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*arb_map_config = thrd_to_arb_map_sku6;
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break;
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default:
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dev_err(&GET_DEV(accel_dev),
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"The configuration doesn't match any SKU");
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*arb_map_config = NULL;
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}
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return thrd_to_arb_map;
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}
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static u32 get_pf2vf_offset(u32 i)
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