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powerpc/fsl-pci: Fix Class Code of PCIe Root Port
By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
board which has this pre-3.0 controller:
$ lspci -bvnn
00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
!!! Invalid class 0b20 for header type 01
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
Port to the Freescale specific PCIe register 0x474.
With this change lspci -b output is:
$ lspci -bvnn
00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Without any "Invalid class" error. So class code was properly reflected
into standard (read-only) PCI register 0x08.
Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
d18d06ac35
Fix activated by U-Boot stay active also after booting Linux kernel.
But boards which use older U-Boot version without that fix are affected and
still require this fix.
So implement this class code fix also in kernel fsl_pci.c driver.
Cc: stable@vger.kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220706101043.4867-1-pali@kernel.org
This commit is contained in:
parent
9257971377
commit
0c551abfa0
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@ -522,6 +522,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
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struct resource rsrc;
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const int *bus_range;
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u8 hdr_type, progif;
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u32 class_code;
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struct device_node *dev;
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struct ccsr_pci __iomem *pci;
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u16 temp;
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@ -595,6 +596,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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/* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
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if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
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early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
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class_code &= 0xff;
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class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
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early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
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}
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} else {
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/*
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* Set PBFR(PCI Bus Function Register)[10] = 1 to
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@ -18,6 +18,7 @@ struct platform_device;
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
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#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
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#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
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#define PIWAR_EN 0x80000000 /* Enable */
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