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irqchip/gic-v4.1: Reduce the delay when polling GICR_VPENDBASER.Dirty

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The 10us delay of the poll on the GICR_VPENDBASER.Dirty bit is too
high, which might greatly affect the total scheduling latency of a
vCPU in our measurement. So we reduce it to 1 to lessen the impact.

Signed-off-by: Shenming Lu <lushenming@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201128141857.983-2-lushenming@huawei.com
This commit is contained in:
Shenming Lu 2020-11-28 22:18:56 +08:00 committed by Marc Zyngier
parent 3841245e84
commit 0b39498230
1 changed files with 1 additions and 1 deletions
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2
drivers/irqchip/irq-gic-v3-its.c
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@ -3808,7 +3808,7 @@ static void its_wait_vpt_parse_complete(void)
WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
val,
!(val & GICR_VPENDBASER_Dirty),
10, 500));
1, 500));
}
static void its_vpe_schedule(struct its_vpe *vpe)