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synced 2024-09-06 18:01:05 +00:00
MIPS: Add new GIC clockevent driver.
Add new clockevent driver that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Raghu Gandham <Raghu.Gandham@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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@ -912,6 +912,9 @@ config CEVT_GT641XX
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config CEVT_R4K
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bool
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config CEVT_GIC
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bool
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config CEVT_SB1250
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bool
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@ -1819,6 +1822,15 @@ config FORCE_MAX_ZONEORDER
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The page size is not necessarily 4KB. Keep this in mind
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when choosing a value for this option.
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config CEVT_GIC
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bool "Use GIC global counter for clock events"
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depends on IRQ_GIC && !(MIPS_SEAD3 || MIPS_MT_SMTC)
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help
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Use the GIC global counter for the clock events. The R4K clock
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event driver is always present, so if the platform ends up not
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detecting a GIC, it will fall back to the R4K timer for the
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generation of clock events.
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config BOARD_SCACHE
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bool
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@ -202,7 +202,7 @@
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#define GIC_VPE_WD_COUNT0_OFS 0x0094
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#define GIC_VPE_WD_INITIAL0_OFS 0x0098
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#define GIC_VPE_COMPARE_LO_OFS 0x00a0
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#define GIC_VPE_COMPARE_HI 0x00a4
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#define GIC_VPE_COMPARE_HI_OFS 0x00a4
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#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
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#define GIC_VPE_EIC_SS(intr) \
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@ -373,7 +373,10 @@ extern void gic_init(unsigned long gic_base_addr,
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unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
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unsigned int intrmap_size, unsigned int irqbase);
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extern void gic_clocksource_init(unsigned int);
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extern unsigned int gic_compare_int (void);
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extern cycle_t gic_read_count(void);
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extern cycle_t gic_read_compare(void);
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extern void gic_write_compare(cycle_t cnt);
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extern void gic_send_ipi(unsigned int intr);
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extern unsigned int plat_ipi_call_int_xlate(unsigned int);
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extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
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@ -53,11 +53,14 @@ extern int (*perf_irq)(void);
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extern unsigned int __weak get_c0_compare_int(void);
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extern int r4k_clockevent_init(void);
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extern int smtc_clockevent_init(void);
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extern int gic_clockevent_init(void);
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static inline int mips_clockevent_init(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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return smtc_clockevent_init();
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#elif defined(CONFIG_CEVT_GIC)
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return (gic_clockevent_init() | r4k_clockevent_init());
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#elif defined(CONFIG_CEVT_R4K)
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return r4k_clockevent_init();
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#else
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@ -19,6 +19,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
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obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
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obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
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obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
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obj-$(CONFIG_CEVT_GIC) += cevt-gic.o
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obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
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obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
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104
arch/mips/kernel/cevt-gic.c
Normal file
104
arch/mips/kernel/cevt-gic.c
Normal file
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@ -0,0 +1,104 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Imagination Technologies Ltd.
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/time.h>
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#include <asm/gic.h>
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#include <asm/mips-boards/maltaint.h>
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DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
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int gic_timer_irq_installed;
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static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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u64 cnt;
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int res;
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cnt = gic_read_count();
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cnt += (u64)delta;
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gic_write_compare(cnt);
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res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
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return res;
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}
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void gic_set_clock_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Nothing to do ... */
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}
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irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd;
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int cpu = smp_processor_id();
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gic_write_compare(gic_read_compare());
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cd = &per_cpu(gic_clockevent_device, cpu);
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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struct irqaction gic_compare_irqaction = {
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.handler = gic_compare_interrupt,
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.flags = IRQF_PERCPU | IRQF_TIMER,
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.name = "timer",
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};
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void gic_event_handler(struct clock_event_device *dev)
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{
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}
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int __cpuinit gic_clockevent_init(void)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq;
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if (!cpu_has_counter || !gic_frequency)
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return -ENXIO;
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irq = MIPS_GIC_IRQ_BASE;
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cd = &per_cpu(gic_clockevent_device, cpu);
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cd->name = "MIPS GIC";
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cd->features = CLOCK_EVT_FEAT_ONESHOT;
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clockevent_set_clock(cd, gic_frequency);
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/* Calculate the min / max delta */
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = gic_next_event;
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cd->set_mode = gic_set_clock_mode;
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cd->event_handler = gic_event_handler;
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clockevents_register_device(cd);
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_MAP), 0x80000002);
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), GIC_VPE_SMASK_CMP_MSK);
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if (gic_timer_irq_installed)
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return 0;
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gic_timer_irq_installed = 1;
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setup_irq(irq, &gic_compare_irqaction);
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irq_set_handler(irq, handle_percpu_irq);
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return 0;
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}
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@ -72,6 +72,9 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
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/* Clear Count/Compare Interrupt */
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write_c0_compare(read_c0_compare());
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cd = &per_cpu(mips_clockevent_device, cpu);
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#ifdef CONFIG_CEVT_GIC
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if (!gic_present)
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#endif
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cd->event_handler(cd);
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}
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@ -203,6 +206,9 @@ int __cpuinit r4k_clockevent_init(void)
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cd->set_mode = mips_set_clock_mode;
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cd->event_handler = mips_event_handler;
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#ifdef CONFIG_CEVT_GIC
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if (!gic_present)
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#endif
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clockevents_register_device(cd);
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if (cp0_timer_irq_installed)
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@ -33,7 +33,7 @@ static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static struct gic_pending_regs pending_regs[NR_CPUS];
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static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
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#ifdef CONFIG_CSRC_GIC
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#if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
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cycle_t gic_read_count(void)
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{
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unsigned int hi, hi2, lo;
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return (((cycle_t) hi) << 32) + lo;
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}
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void gic_write_compare(cycle_t cnt)
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{
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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}
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cycle_t gic_read_compare(void)
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{
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unsigned int hi, lo;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
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return (((cycle_t) hi) << 32) + lo;
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}
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#endif
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unsigned int gic_get_timer_pending(void)
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}
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}
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unsigned int gic_compare_int(void)
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{
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unsigned int pending;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
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if (pending & GIC_VPE_PEND_CMP_MSK)
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return 1;
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else
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return 0;
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}
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unsigned int gic_get_int(void)
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{
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unsigned int i;
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@ -133,6 +133,9 @@ static void malta_ipi_irqdispatch(void)
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{
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int irq;
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if (gic_compare_int())
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do_IRQ(MIPS_GIC_IRQ_BASE);
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irq = gic_get_int();
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if (irq < 0)
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return; /* interrupt has already been cleared */
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