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clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

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The USB and PCIE pipe clocks are sourced from external clocks
inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
clocks is dependent on PHY initialization sequence hence
update halt_check to BRANCH_HALT_SKIP for these clocks so
that clock status bit is not polled when enabling or disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Manu Gautam 2018-05-03 02:36:08 +05:30 committed by Stephen Boyd
parent 7d99ced8f4
commit 096abdc296
1 changed files with 4 additions and 0 deletions
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4
drivers/clk/qcom/gcc-msm8996.c
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@ -1418,6 +1418,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
@ -2472,6 +2473,7 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6b018,
.enable_mask = BIT(0),
@ -2547,6 +2549,7 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x6d018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6d018,
.enable_mask = BIT(0),
@ -2622,6 +2625,7 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x6e018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6e018,
.enable_mask = BIT(0),