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https://github.com/torvalds/linux
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ASoC: fsl: Add i2s and pcm drivers for LPC32xx CPUs
This driver was ported from an old version in linux 2.6.27 and adjusted for the new ASoC framework and DMA API. Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Link: https://patch.msgid.link/20240627150046.258795-12-piotr.wojtaszczyk@timesys.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Piotr Wojtaszczyk
Mark Brown
parent
752fea92d9
commit
0959de657a
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@ -8917,6 +8917,7 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers)
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L: linuxppc-dev@lists.ozlabs.org
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S: Maintained
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F: Documentation/devicetree/bindings/sound/nxp,lpc3220-i2s.yaml
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F: sound/soc/fsl/lpc3xxx-*
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FREESCALE SOC SOUND QMC DRIVER
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M: Herve Codina <herve.codina@bootlin.com>
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@ -131,6 +131,13 @@ config SND_SOC_FSL_RPMSG
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This option is only useful for out-of-tree drivers since
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in-tree drivers select it automatically.
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config SND_SOC_FSL_LPC3XXX
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tristate "SoC Audio for NXP LPC32XX CPUs"
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depends on ARCH_LPC32XX || COMPILE_TEST
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select SND_SOC_GENERIC_DMAENGINE_PCM
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help
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Say Y or M if you want to add support for the LPC3XXX I2S interface.
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config SND_SOC_IMX_PCM_DMA
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tristate
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select SND_SOC_GENERIC_DMAENGINE_PCM
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@ -11,6 +11,7 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
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snd-soc-fsl-audmix-y := fsl_audmix.o
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snd-soc-fsl-asoc-card-y := fsl-asoc-card.o
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snd-soc-fsl-asrc-y := fsl_asrc.o fsl_asrc_dma.o
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snd-soc-fsl-lpc3xxx-y := lpc3xxx-pcm.o lpc3xxx-i2s.o
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snd-soc-fsl-sai-y := fsl_sai.o
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snd-soc-fsl-ssi-y := fsl_ssi.o
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snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) += fsl_ssi_dbg.o
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@ -29,6 +30,7 @@ snd-soc-fsl-qmc-audio-y := fsl_qmc_audio.o
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obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
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obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
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obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o
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obj-$(CONFIG_SND_SOC_FSL_LPC3XXX) += snd-soc-fsl-lpc3xxx.o
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obj-$(CONFIG_SND_SOC_FSL_SAI) += snd-soc-fsl-sai.o
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obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
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obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
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375
sound/soc/fsl/lpc3xxx-i2s.c
Normal file
375
sound/soc/fsl/lpc3xxx-i2s.c
Normal file
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@ -0,0 +1,375 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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//
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// Author: Kevin Wells <kevin.wells@nxp.com>
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//
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// Copyright (C) 2008 NXP Semiconductors
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// Copyright 2023 Timesys Corporation <piotr.wojtaszczyk@timesys.com>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include "lpc3xxx-i2s.h"
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#define I2S_PLAYBACK_FLAG 0x1
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#define I2S_CAPTURE_FLAG 0x2
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#define LPC3XXX_I2S_RATES ( \
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SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
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SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
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#define LPC3XXX_I2S_FORMATS ( \
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SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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static void __lpc3xxx_find_clkdiv(u32 *clkx, u32 *clky, int freq, int xbytes, u32 clkrate)
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{
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u32 i2srate;
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u32 idxx, idyy;
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u32 savedbitclkrate, diff, trate, baseclk;
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/* Adjust rate for sample size (bits) and 2 channels and offset for
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* divider in clock output
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*/
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i2srate = (freq / 100) * 2 * (8 * xbytes);
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i2srate = i2srate << 1;
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clkrate = clkrate / 100;
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baseclk = clkrate;
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*clkx = 1;
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*clky = 1;
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/* Find the best divider */
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*clkx = *clky = 0;
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savedbitclkrate = 0;
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diff = ~0;
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for (idxx = 1; idxx < 0xFF; idxx++) {
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for (idyy = 1; idyy < 0xFF; idyy++) {
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trate = (baseclk * idxx) / idyy;
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if (abs(trate - i2srate) < diff) {
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diff = abs(trate - i2srate);
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savedbitclkrate = trate;
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*clkx = idxx;
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*clky = idyy;
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}
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}
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}
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}
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static int lpc3xxx_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(cpu_dai);
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struct device *dev = i2s_info_p->dev;
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u32 flag;
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int ret = 0;
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guard(mutex)(&i2s_info_p->lock);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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flag = I2S_PLAYBACK_FLAG;
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else
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flag = I2S_CAPTURE_FLAG;
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if (flag & i2s_info_p->streams_in_use) {
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dev_warn(dev, "I2S channel is busy\n");
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ret = -EBUSY;
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return ret;
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}
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if (i2s_info_p->streams_in_use == 0) {
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ret = clk_prepare_enable(i2s_info_p->clk);
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if (ret) {
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dev_err(dev, "Can't enable clock, err=%d\n", ret);
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return ret;
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}
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}
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i2s_info_p->streams_in_use |= flag;
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return 0;
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}
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static void lpc3xxx_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(cpu_dai);
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struct regmap *regs = i2s_info_p->regs;
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const u32 stop_bits = (LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP);
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u32 flag;
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guard(mutex)(&i2s_info_p->lock);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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flag = I2S_PLAYBACK_FLAG;
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regmap_write(regs, LPC3XXX_REG_I2S_TX_RATE, 0);
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regmap_update_bits(regs, LPC3XXX_REG_I2S_DAO, stop_bits, stop_bits);
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} else {
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flag = I2S_CAPTURE_FLAG;
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regmap_write(regs, LPC3XXX_REG_I2S_RX_RATE, 0);
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regmap_update_bits(regs, LPC3XXX_REG_I2S_DAI, stop_bits, stop_bits);
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}
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i2s_info_p->streams_in_use &= ~flag;
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if (i2s_info_p->streams_in_use == 0)
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clk_disable_unprepare(i2s_info_p->clk);
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}
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static int lpc3xxx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(cpu_dai);
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/* Will use in HW params later */
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i2s_info_p->freq = freq;
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return 0;
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}
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static int lpc3xxx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(cpu_dai);
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struct device *dev = i2s_info_p->dev;
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if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S) {
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dev_warn(dev, "unsupported bus format %d\n", fmt);
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return -EINVAL;
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}
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if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) {
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dev_warn(dev, "unsupported clock provider %d\n", fmt);
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return -EINVAL;
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}
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return 0;
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}
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static int lpc3xxx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(cpu_dai);
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struct device *dev = i2s_info_p->dev;
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struct regmap *regs = i2s_info_p->regs;
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int xfersize;
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u32 tmp, clkx, clky;
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tmp = LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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tmp |= LPC3XXX_I2S_WW8 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW8_HP);
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xfersize = 1;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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tmp |= LPC3XXX_I2S_WW16 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW16_HP);
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xfersize = 2;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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tmp |= LPC3XXX_I2S_WW32 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW32_HP);
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xfersize = 4;
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break;
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default:
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dev_warn(dev, "Unsupported audio data format %d\n", params_format(params));
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return -EINVAL;
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}
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if (params_channels(params) == 1)
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tmp |= LPC3XXX_I2S_MONO;
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__lpc3xxx_find_clkdiv(&clkx, &clky, i2s_info_p->freq, xfersize, i2s_info_p->clkrate);
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dev_dbg(dev, "Stream : %s\n",
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substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "playback" : "capture");
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dev_dbg(dev, "Desired clock rate : %d\n", i2s_info_p->freq);
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dev_dbg(dev, "Base clock rate : %d\n", i2s_info_p->clkrate);
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dev_dbg(dev, "Transfer size (bytes) : %d\n", xfersize);
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dev_dbg(dev, "Clock divider (x) : %d\n", clkx);
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dev_dbg(dev, "Clock divider (y) : %d\n", clky);
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dev_dbg(dev, "Channels : %d\n", params_channels(params));
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dev_dbg(dev, "Data format : %s\n", "I2S");
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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regmap_write(regs, LPC3XXX_REG_I2S_DMA1,
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LPC3XXX_I2S_DMA1_TX_EN | LPC3XXX_I2S_DMA0_TX_DEPTH(4));
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regmap_write(regs, LPC3XXX_REG_I2S_TX_RATE, (clkx << 8) | clky);
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regmap_write(regs, LPC3XXX_REG_I2S_DAO, tmp);
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} else {
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regmap_write(regs, LPC3XXX_REG_I2S_DMA0,
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LPC3XXX_I2S_DMA0_RX_EN | LPC3XXX_I2S_DMA1_RX_DEPTH(4));
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regmap_write(regs, LPC3XXX_REG_I2S_RX_RATE, (clkx << 8) | clky);
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regmap_write(regs, LPC3XXX_REG_I2S_DAI, tmp);
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}
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return 0;
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}
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static int lpc3xxx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(cpu_dai);
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struct regmap *regs = i2s_info_p->regs;
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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regmap_update_bits(regs, LPC3XXX_REG_I2S_DAO,
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LPC3XXX_I2S_STOP, LPC3XXX_I2S_STOP);
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else
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regmap_update_bits(regs, LPC3XXX_REG_I2S_DAI,
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LPC3XXX_I2S_STOP, LPC3XXX_I2S_STOP);
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break;
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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regmap_update_bits(regs, LPC3XXX_REG_I2S_DAO,
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(LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP), 0);
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else
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regmap_update_bits(regs, LPC3XXX_REG_I2S_DAI,
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(LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP), 0);
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int lpc3xxx_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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struct lpc3xxx_i2s_info *i2s_info_p = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai, &i2s_info_p->playback_dma_config,
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&i2s_info_p->capture_dma_config);
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return 0;
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}
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const struct snd_soc_dai_ops lpc3xxx_i2s_dai_ops = {
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.probe = lpc3xxx_i2s_dai_probe,
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.startup = lpc3xxx_i2s_startup,
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.shutdown = lpc3xxx_i2s_shutdown,
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.trigger = lpc3xxx_i2s_trigger,
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.hw_params = lpc3xxx_i2s_hw_params,
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.set_sysclk = lpc3xxx_i2s_set_dai_sysclk,
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.set_fmt = lpc3xxx_i2s_set_dai_fmt,
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};
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struct snd_soc_dai_driver lpc3xxx_i2s_dai_driver = {
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.playback = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = LPC3XXX_I2S_RATES,
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.formats = LPC3XXX_I2S_FORMATS,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = LPC3XXX_I2S_RATES,
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.formats = LPC3XXX_I2S_FORMATS,
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},
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.ops = &lpc3xxx_i2s_dai_ops,
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.symmetric_rate = 1,
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.symmetric_channels = 1,
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.symmetric_sample_bits = 1,
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};
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static const struct snd_soc_component_driver lpc32xx_i2s_component = {
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.name = "lpc32xx-i2s",
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.legacy_dai_naming = 1,
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};
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static const struct regmap_config lpc32xx_i2s_regconfig = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = LPC3XXX_REG_I2S_RX_RATE,
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};
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static int lpc32xx_i2s_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct lpc3xxx_i2s_info *i2s_info_p;
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struct resource *res;
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void __iomem *iomem;
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int ret;
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i2s_info_p = devm_kzalloc(dev, sizeof(*i2s_info_p), GFP_KERNEL);
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if (!i2s_info_p)
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return -ENOMEM;
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platform_set_drvdata(pdev, i2s_info_p);
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i2s_info_p->dev = dev;
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iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(iomem))
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return dev_err_probe(dev, PTR_ERR(iomem), "Can't map registers\n");
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i2s_info_p->regs = devm_regmap_init_mmio(dev, iomem, &lpc32xx_i2s_regconfig);
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if (IS_ERR(i2s_info_p->regs))
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return dev_err_probe(dev, PTR_ERR(i2s_info_p->regs),
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"failed to init register map: %d\n", ret);
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i2s_info_p->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(i2s_info_p->clk))
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return dev_err_probe(dev, PTR_ERR(i2s_info_p->clk), "Can't get clock\n");
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i2s_info_p->clkrate = clk_get_rate(i2s_info_p->clk);
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if (i2s_info_p->clkrate == 0)
|
||||
return dev_err_probe(dev, -EINVAL, "Invalid returned clock rate\n");
|
||||
|
||||
mutex_init(&i2s_info_p->lock);
|
||||
|
||||
ret = devm_snd_soc_register_component(dev, &lpc32xx_i2s_component,
|
||||
&lpc3xxx_i2s_dai_driver, 1);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Can't register cpu_dai component\n");
|
||||
|
||||
i2s_info_p->playback_dma_config.addr = (dma_addr_t)(res->start + LPC3XXX_REG_I2S_TX_FIFO);
|
||||
i2s_info_p->playback_dma_config.maxburst = 4;
|
||||
|
||||
i2s_info_p->capture_dma_config.addr = (dma_addr_t)(res->start + LPC3XXX_REG_I2S_RX_FIFO);
|
||||
i2s_info_p->capture_dma_config.maxburst = 4;
|
||||
|
||||
ret = lpc3xxx_pcm_register(pdev);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Can't register pcm component\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id lpc32xx_i2s_match[] = {
|
||||
{ .compatible = "nxp,lpc3220-i2s" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpc32xx_i2s_match);
|
||||
|
||||
static struct platform_driver lpc32xx_i2s_driver = {
|
||||
.probe = lpc32xx_i2s_probe,
|
||||
.driver = {
|
||||
.name = "lpc3xxx-i2s",
|
||||
.of_match_table = lpc32xx_i2s_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(lpc32xx_i2s_driver);
|
||||
|
||||
MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
|
||||
MODULE_AUTHOR("Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>");
|
||||
MODULE_DESCRIPTION("ASoC LPC3XXX I2S interface");
|
||||
MODULE_LICENSE("GPL");
|
||||
79
sound/soc/fsl/lpc3xxx-i2s.h
Normal file
79
sound/soc/fsl/lpc3xxx-i2s.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2008 NXP Semiconductors
|
||||
* Copyright 2023 Timesys Corporation <piotr.wojtaszczyk@timesys.com>
|
||||
*/
|
||||
|
||||
#ifndef __SOUND_SOC_LPC3XXX_I2S_H
|
||||
#define __SOUND_SOC_LPC3XXX_I2S_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
struct lpc3xxx_i2s_info {
|
||||
struct device *dev;
|
||||
struct clk *clk;
|
||||
struct mutex lock; /* To serialize user-space access */
|
||||
struct regmap *regs;
|
||||
u32 streams_in_use;
|
||||
u32 clkrate;
|
||||
int freq;
|
||||
struct snd_dmaengine_dai_dma_data playback_dma_config;
|
||||
struct snd_dmaengine_dai_dma_data capture_dma_config;
|
||||
};
|
||||
|
||||
int lpc3xxx_pcm_register(struct platform_device *pdev);
|
||||
|
||||
/* I2S controller register offsets */
|
||||
#define LPC3XXX_REG_I2S_DAO 0x00
|
||||
#define LPC3XXX_REG_I2S_DAI 0x04
|
||||
#define LPC3XXX_REG_I2S_TX_FIFO 0x08
|
||||
#define LPC3XXX_REG_I2S_RX_FIFO 0x0C
|
||||
#define LPC3XXX_REG_I2S_STAT 0x10
|
||||
#define LPC3XXX_REG_I2S_DMA0 0x14
|
||||
#define LPC3XXX_REG_I2S_DMA1 0x18
|
||||
#define LPC3XXX_REG_I2S_IRQ 0x1C
|
||||
#define LPC3XXX_REG_I2S_TX_RATE 0x20
|
||||
#define LPC3XXX_REG_I2S_RX_RATE 0x24
|
||||
|
||||
/* i2s_daO i2s_dai register definitions */
|
||||
#define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */
|
||||
#define LPC3XXX_I2S_WW16 FIELD_PREP(0x3, 1) /* Word width is 16bit */
|
||||
#define LPC3XXX_I2S_WW32 FIELD_PREP(0x3, 3) /* Word width is 32bit */
|
||||
#define LPC3XXX_I2S_MONO BIT(2) /* Mono */
|
||||
#define LPC3XXX_I2S_STOP BIT(3) /* Stop, diables the access to FIFO, mutes the channel */
|
||||
#define LPC3XXX_I2S_RESET BIT(4) /* Reset the channel */
|
||||
#define LPC3XXX_I2S_WS_SEL BIT(5) /* Channel Master(0) or slave(1) mode select */
|
||||
#define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
|
||||
#define LPC3XXX_I2S_MUTE BIT(15) /* Mute the channel, Transmit channel only */
|
||||
|
||||
#define LPC3XXX_I2S_WW32_HP 0x1f /* Word select half period for 32bit word width */
|
||||
#define LPC3XXX_I2S_WW16_HP 0x0f /* Word select half period for 16bit word width */
|
||||
#define LPC3XXX_I2S_WW8_HP 0x7 /* Word select half period for 8bit word width */
|
||||
|
||||
/* i2s_stat register definitions */
|
||||
#define LPC3XXX_I2S_IRQ_STAT BIT(0)
|
||||
#define LPC3XXX_I2S_DMA0_REQ BIT(1)
|
||||
#define LPC3XXX_I2S_DMA1_REQ BIT(2)
|
||||
|
||||
/* i2s_dma0 Configuration register definitions */
|
||||
#define LPC3XXX_I2S_DMA0_RX_EN BIT(0) /* Enable RX DMA1 */
|
||||
#define LPC3XXX_I2S_DMA0_TX_EN BIT(1) /* Enable TX DMA1 */
|
||||
#define LPC3XXX_I2S_DMA0_RX_DEPTH(s) FIELD_PREP(0xF00, s) /* Set the DMA1 RX Request level */
|
||||
#define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA1 TX Request level */
|
||||
|
||||
/* i2s_dma1 Configuration register definitions */
|
||||
#define LPC3XXX_I2S_DMA1_RX_EN BIT(0) /* Enable RX DMA1 */
|
||||
#define LPC3XXX_I2S_DMA1_TX_EN BIT(1) /* Enable TX DMA1 */
|
||||
#define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 RX Request level */
|
||||
#define LPC3XXX_I2S_DMA1_TX_DEPTH(s) FIELD_PREP(0x70000, s) /* Set the DMA1 TX Request level */
|
||||
|
||||
/* i2s_irq register definitions */
|
||||
#define LPC3XXX_I2S_RX_IRQ_EN BIT(0) /* Enable RX IRQ */
|
||||
#define LPC3XXX_I2S_TX_IRQ_EN BIT(1) /* Enable TX IRQ */
|
||||
#define LPC3XXX_I2S_IRQ_RX_DEPTH(s) FIELD_PREP(0xFF00, s) /* valid values ar 0 to 7 */
|
||||
#define LPC3XXX_I2S_IRQ_TX_DEPTH(s) FIELD_PREP(0xFF0000, s) /* valid values ar 0 to 7 */
|
||||
|
||||
#endif
|
||||
72
sound/soc/fsl/lpc3xxx-pcm.c
Normal file
72
sound/soc/fsl/lpc3xxx-pcm.c
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
//
|
||||
// Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
//
|
||||
// Copyright (C) 2008 NXP Semiconductors
|
||||
// Copyright 2023 Timesys Corporation <piotr.wojtaszczyk@timesys.com>
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
#include <sound/soc.h>
|
||||
|
||||
#include "lpc3xxx-i2s.h"
|
||||
|
||||
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
|
||||
SNDRV_PCM_FMTBIT_U8 | \
|
||||
SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_U16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | \
|
||||
SNDRV_PCM_FMTBIT_U24_LE | \
|
||||
SNDRV_PCM_FMTBIT_S32_LE | \
|
||||
SNDRV_PCM_FMTBIT_U32_LE | \
|
||||
SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
|
||||
|
||||
static const struct snd_pcm_hardware lpc3xxx_pcm_hardware = {
|
||||
.info = (SNDRV_PCM_INFO_MMAP |
|
||||
SNDRV_PCM_INFO_MMAP_VALID |
|
||||
SNDRV_PCM_INFO_INTERLEAVED |
|
||||
SNDRV_PCM_INFO_BLOCK_TRANSFER |
|
||||
SNDRV_PCM_INFO_PAUSE |
|
||||
SNDRV_PCM_INFO_RESUME),
|
||||
.formats = STUB_FORMATS,
|
||||
.period_bytes_min = 128,
|
||||
.period_bytes_max = 2048,
|
||||
.periods_min = 2,
|
||||
.periods_max = 1024,
|
||||
.buffer_bytes_max = 128 * 1024
|
||||
};
|
||||
|
||||
static const struct snd_dmaengine_pcm_config lpc3xxx_dmaengine_pcm_config = {
|
||||
.pcm_hardware = &lpc3xxx_pcm_hardware,
|
||||
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
|
||||
.compat_filter_fn = pl08x_filter_id,
|
||||
.prealloc_buffer_size = 128 * 1024,
|
||||
};
|
||||
|
||||
const struct snd_soc_component_driver lpc3xxx_soc_platform_driver = {
|
||||
.name = "lpc32xx-pcm",
|
||||
};
|
||||
|
||||
int lpc3xxx_pcm_register(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, &lpc3xxx_dmaengine_pcm_config, 0);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register dmaengine: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_snd_soc_register_component(&pdev->dev, &lpc3xxx_soc_platform_driver,
|
||||
NULL, 0);
|
||||
}
|
||||
EXPORT_SYMBOL(lpc3xxx_pcm_register);
|
||||
Loading…
Reference in a new issue